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83 lines
2.8 KiB
Python
83 lines
2.8 KiB
Python
2 years ago
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from amaranth import *
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from amaranth.asserts import *
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from amaranth.utils import log2_int
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from amaranth_soc import wishbone
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from power_fv.check.storage import DataStorageCheck, DataStorageTestbench, DataStorageModel
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from ..core import *
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__all__ = [
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"DataStorageCheck_Microwatt", "DataStorageTestbench_Microwatt", "DataStorageModel_Microwatt",
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]
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class DataStorageCheck_Microwatt(DataStorageCheck, name=("microwatt", "storage", "data")):
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def __init__(self, *, depth, skip, core, **kwargs):
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if not isinstance(core, MicrowattCore):
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raise TypeError("Core must be an instance of MicrowattCore, not {!r}"
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.format(core))
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super().__init__(depth=depth, skip=skip, core=core, **kwargs)
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def testbench(self):
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return DataStorageTestbench_Microwatt(self)
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class DataStorageTestbench_Microwatt(DataStorageTestbench):
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def storage(self):
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return DataStorageModel_Microwatt()
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class DataStorageModel_Microwatt(DataStorageModel, Elaboratable):
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def __init__(self):
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self.addr = Signal(64)
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self._dbus = wishbone.Interface(addr_width=29, data_width=64, granularity=8,
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features=("stall",))
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def connect(self, dut):
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assert isinstance(dut, MicrowattWrapper)
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assert dut.wb_data.addr_width == self._dbus.addr_width
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assert dut.wb_data.data_width == self._dbus.data_width
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assert dut.wb_data.granularity == self._dbus.granularity
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return self._dbus.eq(dut.wb_data)
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def elaborate(self, platform):
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m = Module()
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dbus_read = Signal()
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dbus_write = Signal()
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m.d.comb += [
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dbus_read .eq(self._dbus.cyc & self._dbus.stb & self._dbus.ack),
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dbus_write.eq(self._dbus.cyc & self._dbus.stb & self._dbus.ack & self._dbus.we),
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Assume(self._dbus.ack.implies(Past(self._dbus.cyc) & self._dbus.cyc)),
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Assume(self._dbus.ack.implies(Past(self._dbus.stb) & self._dbus.stb)),
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Assume(self._dbus.ack.implies(~Past(self._dbus.ack))),
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]
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with m.If(self._dbus.cyc & self._dbus.stb):
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m.d.comb += Assume(self._dbus.stall == ~self._dbus.ack)
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addr_lsb = log2_int(len(self._dbus.sel))
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addr_hit = Signal()
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value = Signal(64)
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m.d.comb += [
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self.addr.eq(Cat(AnyConst(32), Const(0, 32))),
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addr_hit.eq(self._dbus.adr == self.addr[addr_lsb:32]),
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]
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with m.If(dbus_read & addr_hit & ~ResetSignal("sync")):
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m.d.comb += Assume(self._dbus.dat_r == value)
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with m.If(dbus_write & addr_hit):
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for i, sel_bit in enumerate(self._dbus.sel):
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with m.If(sel_bit):
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m.d.sync += value[i*8:i*8+8].eq(self._dbus.dat_w[i*8:i*8+8])
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return m
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