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116 lines
3.4 KiB
Python
116 lines
3.4 KiB
Python
3 years ago
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from amaranth import *
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from amaranth.asserts import *
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from .. import pfv
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__all__ = ["SPRCheck", "SPRCover"]
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class SPRCheck(Elaboratable):
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"""Special Purpose Registers check.
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Checks that reads from supported SPRs are consistent with the last value that was written to
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them.
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"""
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def __init__(self):
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self.pre = Signal()
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self.post = Signal()
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self.pfv = pfv.Interface()
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def elaborate(self, platform):
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m = Module()
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spec_order = AnyConst(self.pfv.order.width)
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lr_written = Signal()
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lr_shadow = Signal(64)
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ctr_written = Signal()
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ctr_shadow = Signal(64)
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xer_written = Signal()
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xer_shadow = Signal(64)
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tar_written = Signal()
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tar_shadow = Signal(64)
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with m.If(self.pfv.stb & (self.pfv.order <= spec_order)):
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with m.If(self.pfv.lr.w_stb):
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m.d.sync += [
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lr_written.eq(1),
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lr_shadow .eq(self.pfv.lr.w_data),
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]
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with m.If(self.pfv.ctr.w_stb):
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m.d.sync += [
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ctr_written.eq(1),
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ctr_shadow .eq(self.pfv.ctr.w_data),
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]
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with m.If(self.pfv.xer.w_stb):
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m.d.sync += [
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xer_written.eq(1),
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xer_shadow .eq(self.pfv.xer.w_data),
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]
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with m.If(self.pfv.tar.w_stb):
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m.d.sync += [
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tar_written.eq(1),
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tar_shadow .eq(self.pfv.tar.w_data),
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]
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with m.If(self.post):
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m.d.sync += [
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Assume(Past(self.pfv.stb)),
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Assume(Past(self.pfv.order) == spec_order),
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]
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with m.If(Past(self.pfv.lr.r_stb)):
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m.d.sync += Assert(Past(lr_shadow) == Past(self.pfv.lr.r_data))
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with m.If(Past(self.pfv.ctr.r_stb)):
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m.d.sync += Assert(Past(ctr_shadow) == Past(self.pfv.ctr.r_data))
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with m.If(Past(self.pfv.xer.r_stb)):
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m.d.sync += Assert(Past(xer_shadow) == Past(self.pfv.xer.r_data))
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with m.If(Past(self.pfv.tar.r_stb)):
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m.d.sync += Assert(Past(tar_shadow) == Past(self.pfv.tar.r_data))
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return m
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class SPRCover(Elaboratable):
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def __init__(self):
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self.pre = Signal()
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self.post = Signal()
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self.pfv = pfv.Interface()
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def elaborate(self, platform):
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m = Module()
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insn_count = Signal(range(4))
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lr_written = Signal()
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ctr_written = Signal()
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xer_written = Signal()
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tar_written = Signal()
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with m.If(self.pfv.stb):
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m.d.sync += [
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insn_count .eq(insn_count + 1),
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lr_written .eq(self.pfv.lr .w_stb),
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ctr_written.eq(self.pfv.ctr.w_stb),
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xer_written.eq(self.pfv.xer.w_stb),
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tar_written.eq(self.pfv.tar.w_stb),
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]
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cover_1 = Signal()
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cover_2 = Signal()
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cover_3 = Signal()
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cover_4 = Signal()
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m.d.comb += [
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cover_1.eq((insn_count > 1) & lr_written),
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cover_2.eq((insn_count > 1) & ctr_written),
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cover_3.eq((insn_count > 1) & xer_written),
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cover_4.eq((insn_count > 1) & tar_written),
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Cover(cover_1),
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Cover(cover_2),
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Cover(cover_3),
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Cover(cover_4),
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]
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return m
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