You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
microwatt/litedram/generated/sim
Benjamin Herrenschmidt f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
..
litedram-initmem.vhdl litedram: Fix DRAM init mem using too many address bits 4 years ago
litedram_core.init soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding 4 years ago
litedram_core.v spi: Add booting from flash to litedram init 4 years ago