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158 lines
4.0 KiB
VHDL
158 lines
4.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity icache_tb is
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end icache_tb;
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architecture behave of icache_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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signal i_out : Fetch1ToIcacheType;
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signal i_in : IcacheToDecode1Type;
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signal m_out : MmuToIcacheType;
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant clk_period : time := 10 ns;
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begin
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icache0: entity work.icache
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generic map(
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LINE_SIZE => 64,
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NUM_LINES => 4
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)
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port map(
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clk => clk,
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rst => rst,
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i_in => i_out,
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i_out => i_in,
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m_in => m_out,
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stall_in => '0',
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flush_in => '0',
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inval_in => '0',
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wishbone_out => wb_bram_in,
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wishbone_in => wb_bram_out
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);
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-- BRAM Memory slave
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bram0: entity work.wishbone_bram_wrapper
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generic map(
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MEMORY_SIZE => 1024,
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RAM_INIT_FILE => "icache_test.bin"
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)
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port map(
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clk => clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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rst_process: process
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begin
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rst <= '1';
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wait for 2*clk_period;
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rst <= '0';
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wait;
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end process;
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stim: process
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begin
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i_out.req <= '0';
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i_out.nia <= (others => '0');
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i_out.stop_mark <= '0';
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i_out.priv_mode <= '1';
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i_out.virt_mode <= '0';
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i_out.big_endian <= '0';
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m_out.tlbld <= '0';
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m_out.tlbie <= '0';
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m_out.addr <= (others => '0');
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m_out.pte <= (others => '0');
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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i_out.req <= '1';
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i_out.nia <= x"0000000000000004";
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wait for 30*clk_period;
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wait until rising_edge(clk);
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assert i_in.valid = '1' severity failure;
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assert i_in.insn = x"00000001"
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report "insn @" & to_hstring(i_out.nia) &
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"=" & to_hstring(i_in.insn) &
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" expected 00000001"
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severity failure;
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i_out.req <= '0';
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wait until rising_edge(clk);
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-- hit
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i_out.req <= '1';
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i_out.nia <= x"0000000000000008";
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert i_in.valid = '1' severity failure;
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assert i_in.insn = x"00000002"
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report "insn @" & to_hstring(i_out.nia) &
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"=" & to_hstring(i_in.insn) &
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" expected 00000002"
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severity failure;
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wait until rising_edge(clk);
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-- another miss
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i_out.req <= '1';
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i_out.nia <= x"0000000000000040";
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wait for 30*clk_period;
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wait until rising_edge(clk);
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assert i_in.valid = '1' severity failure;
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assert i_in.insn = x"00000010"
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report "insn @" & to_hstring(i_out.nia) &
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"=" & to_hstring(i_in.insn) &
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" expected 00000010"
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severity failure;
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-- test something that aliases
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i_out.req <= '1';
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i_out.nia <= x"0000000000000100";
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert i_in.valid = '0' severity failure;
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wait until rising_edge(clk);
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wait for 30*clk_period;
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wait until rising_edge(clk);
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assert i_in.valid = '1' severity failure;
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assert i_in.insn = x"00000040"
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report "insn @" & to_hstring(i_out.nia) &
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"=" & to_hstring(i_in.insn) &
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" expected 00000040"
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severity failure;
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i_out.req <= '0';
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std.env.finish;
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end process;
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end;
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