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210 lines
5.6 KiB
VHDL
210 lines
5.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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use std.textio.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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-- 0x00000000: Main memory (1 MB)
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-- 0xc0002000: UART0 (for host communication)
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entity soc is
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generic (
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MEMORY_SIZE : positive;
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RAM_INIT_FILE : string;
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RESET_LOW : boolean;
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SIM : boolean
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);
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port(
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rst : in std_ulogic;
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system_clk : in std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic
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);
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end entity soc;
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architecture behaviour of soc is
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-- Wishbone master signals:
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signal wishbone_dcore_in : wishbone_slave_out;
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signal wishbone_dcore_out : wishbone_master_out;
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signal wishbone_icore_in : wishbone_slave_out;
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signal wishbone_icore_out : wishbone_master_out;
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signal wishbone_debug_in : wishbone_slave_out;
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signal wishbone_debug_out : wishbone_master_out;
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-- Wishbone master (output of arbiter):
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signal wb_master_in : wishbone_slave_out;
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signal wb_master_out : wishbone_master_out;
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-- UART0 signals:
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signal wb_uart0_in : wishbone_master_out;
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signal wb_uart0_out : wishbone_slave_out;
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signal uart_dat8 : std_ulogic_vector(7 downto 0);
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-- Main memory signals:
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signal wb_bram_in : wishbone_master_out;
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signal wb_bram_out : wishbone_slave_out;
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constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
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-- Core debug signals (used in SIM only)
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signal registers : regfile;
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signal terminate : std_ulogic;
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-- DMI debug bus signals
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signal dmi_addr : std_ulogic_vector(7 downto 0);
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signal dmi_din : std_ulogic_vector(63 downto 0);
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signal dmi_dout : std_ulogic_vector(63 downto 0);
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signal dmi_req : std_ulogic;
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signal dmi_wr : std_ulogic;
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signal dmi_ack : std_ulogic;
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begin
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-- Processor core
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processor: entity work.core
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generic map(
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SIM => SIM
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)
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port map(
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clk => system_clk,
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rst => rst,
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wishbone_insn_in => wishbone_icore_in,
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wishbone_insn_out => wishbone_icore_out,
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wishbone_data_in => wishbone_dcore_in,
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wishbone_data_out => wishbone_dcore_out,
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registers => registers,
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terminate_out => terminate
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);
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-- Wishbone bus master arbiter & mux
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wishbone_arbiter_0: entity work.wishbone_arbiter
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port map(
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clk => system_clk, rst => rst,
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wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
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wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
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wb3_in => wishbone_debug_out, wb3_out => wishbone_debug_in,
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wb_out => wb_master_out, wb_in => wb_master_in
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);
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-- Dummy wishbone debug module
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wishbone_debug_out.cyc <= '0';
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wishbone_debug_out.stb <= '0';
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-- Wishbone slaves address decoder & mux
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slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
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-- Selected slave
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type slave_type is (SLAVE_UART,
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SLAVE_MEMORY,
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SLAVE_NONE);
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variable slave : slave_type;
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begin
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-- Simple address decoder
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slave := SLAVE_NONE;
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if wb_master_out.adr(63 downto 24) = x"0000000000" then
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slave := SLAVE_MEMORY;
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elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
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if wb_master_out.adr(15 downto 12) = x"2" then
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slave := SLAVE_UART;
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end if;
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end if;
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-- Wishbone muxing. Defaults:
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wb_bram_in <= wb_master_out;
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wb_bram_in.cyc <= '0';
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wb_uart0_in <= wb_master_out;
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wb_uart0_in.cyc <= '0';
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case slave is
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when SLAVE_MEMORY =>
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wb_bram_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_bram_out;
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when SLAVE_UART =>
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wb_uart0_in.cyc <= wb_master_out.cyc;
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wb_master_in <= wb_uart0_out;
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when others =>
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wb_master_in.dat <= (others => '1');
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wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
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end case;
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end process slave_intercon;
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-- Simulated memory and UART
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sim_terminate_test: if SIM generate
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-- Dump registers if core terminates
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dump_registers: process(all)
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begin
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if terminate = '1' then
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loop_0: for i in 0 to 31 loop
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report "REG " & to_hstring(registers(i));
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end loop loop_0;
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assert false report "end of test" severity failure;
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end if;
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end process;
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end generate;
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-- UART0 wishbone slave
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-- XXX FIXME: Need a proper wb64->wb8 adapter that
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-- converts SELs into low address bits and muxes
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-- data accordingly (either that or rejects large
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-- cycles).
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uart0: entity work.pp_soc_uart
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generic map(
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FIFO_DEPTH => 32
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)
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port map(
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clk => system_clk,
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reset => rst,
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txd => uart0_txd,
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rxd => uart0_rxd,
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wb_adr_in => wb_uart0_in.adr(11 downto 0),
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wb_dat_in => wb_uart0_in.dat(7 downto 0),
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wb_dat_out => uart_dat8,
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wb_cyc_in => wb_uart0_in.cyc,
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wb_stb_in => wb_uart0_in.stb,
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wb_we_in => wb_uart0_in.we,
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wb_ack_out => wb_uart0_out.ack
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);
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wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
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-- BRAM Memory slave
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bram0: entity work.mw_soc_memory
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE
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)
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port map(
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clk => system_clk,
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rst => rst,
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wishbone_in => wb_bram_in,
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wishbone_out => wb_bram_out
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);
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-- DMI(debug bus) <-> JTAG bridge
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dtm: entity work.dmi_dtm
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generic map(
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ABITS => 8,
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DBITS => 64
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)
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port map(
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sys_clk => system_clk,
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sys_reset => rst,
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dmi_addr => dmi_addr,
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dmi_din => dmi_din,
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dmi_dout => dmi_dout,
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dmi_req => dmi_req,
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dmi_wr => dmi_wr,
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dmi_ack => dmi_ack
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);
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-- Dummy loopback until a debug module is present
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dmi_din <= dmi_dout;
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dmi_ack <= dmi_ack;
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end architecture behaviour;
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