A tiny Open POWER ISA softcore written in VHDL 2008

openpower ppc64le processor vhdl

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Benjamin Herrenschmidt ec1868f7d2 register_file: Move GPRs into distributed RAM The register file is currently implemented as a whole pile of individual 1-bit registers instead of LUT memory which is a huge waste of FPGA space. This is caused by the output signal exposing the register file to the outside world for simulation debug. This removes that output, and moves the dumping of the register file to the register file module itself. This saves about 8% of fpga on the little Arty A7-35T. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
fpga	Improve PLL/MMCM clocks configuration	5 years ago
hello_world	…
scripts	…
sim-unisim	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	Update dependency	5 years ago
README.md	…
common.vhdl	register_file: Move GPRs into distributed RAM	5 years ago
core.vhdl	register_file: Move GPRs into distributed RAM	5 years ago
core_debug.vhdl	…
core_tb.vhdl	…
cr_file.vhdl	…
crhelpers.vhdl	…
decode1.vhdl	…
decode2.vhdl	divider: Do absolute-value ops in divider instead of decode	5 years ago
decode_types.vhdl	…
divider.vhdl	divider: Do absolute-value ops in divider instead of decode	5 years ago
divider_tb.vhdl	divider: Do absolute-value ops in divider instead of decode	5 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	Don't reset JTAG request register asynchronously	5 years ago
execute1.vhdl	execute1: simplify flush_out	5 years ago
execute2.vhdl	…
fetch1.vhdl	Simplify fetch1	5 years ago
fetch2.vhdl	Reformat fetch2	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	…
icache.vhdl	…
icache_tb.vhdl	…
insn_helpers.vhdl	…
loadstore1.vhdl	…
loadstore2.vhdl	loadstore2: Do data formatting after a register stage	5 years ago
microwatt.core	Improve PLL/MMCM clocks configuration	5 years ago
multiply.vhdl	Multiply needs to be 16 stages to fix all timing issues	5 years ago
multiply_tb.vhdl	…
ppc_fx_insns.vhdl	…
register_file.vhdl	register_file: Move GPRs into distributed RAM	5 years ago
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	debug/sim: Make connect/disconnect messages quieter	5 years ago
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
soc.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	…

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)