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These are intended to be combinatorial. The previous code was giving warnings in vivado about registers/latches with no clock defined. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
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fpga | 5 years ago | |
hello_world | 5 years ago | |
scripts | 5 years ago | |
sim-unisim | 5 years ago | |
tests | 5 years ago | |
.gitignore | 5 years ago | |
.travis.yml | 5 years ago | |
LICENSE | 5 years ago | |
Makefile | 5 years ago | |
README.md | 5 years ago | |
common.vhdl | 5 years ago | |
core.vhdl | 5 years ago | |
core_debug.vhdl | 5 years ago | |
core_tb.vhdl | 5 years ago | |
cr_file.vhdl | 5 years ago | |
crhelpers.vhdl | 5 years ago | |
decode1.vhdl | 5 years ago | |
decode2.vhdl | 5 years ago | |
decode_types.vhdl | 5 years ago | |
divider.vhdl | 5 years ago | |
divider_tb.vhdl | 5 years ago | |
dmi_dtm_dummy.vhdl | 5 years ago | |
dmi_dtm_tb.vhdl | 5 years ago | |
dmi_dtm_xilinx.vhdl | 5 years ago | |
execute1.vhdl | 5 years ago | |
execute2.vhdl | 5 years ago | |
fetch1.vhdl | 5 years ago | |
fetch2.vhdl | 5 years ago | |
glibc_random.vhdl | 5 years ago | |
glibc_random_helpers.vhdl | 5 years ago | |
helpers.vhdl | 5 years ago | |
icache.vhdl | 5 years ago | |
icache_tb.vhdl | 5 years ago | |
insn_helpers.vhdl | 5 years ago | |
loadstore1.vhdl | 5 years ago | |
loadstore2.vhdl | 5 years ago | |
microwatt.core | 5 years ago | |
multiply.vhdl | 5 years ago | |
multiply_tb.vhdl | 5 years ago | |
ppc_fx_insns.vhdl | 5 years ago | |
register_file.vhdl | 5 years ago | |
sim_console.vhdl | 5 years ago | |
sim_console_c.c | 5 years ago | |
sim_jtag.vhdl | 5 years ago | |
sim_jtag_socket.vhdl | 5 years ago | |
sim_jtag_socket_c.c | 5 years ago | |
sim_uart.vhdl | 5 years ago | |
simple_ram_behavioural.vhdl | 5 years ago | |
simple_ram_behavioural_helpers.vhdl | 5 years ago | |
simple_ram_behavioural_helpers_c.c | 5 years ago | |
simple_ram_behavioural_tb.bin | 5 years ago | |
simple_ram_behavioural_tb.vhdl | 5 years ago | |
soc.vhdl | 5 years ago | |
wishbone_arbiter.vhdl | 5 years ago | |
wishbone_debug_master.vhdl | 5 years ago | |
wishbone_types.vhdl | 5 years ago | |
writeback.vhdl | 5 years ago |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
- Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)