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653 lines
24 KiB
VHDL
653 lines
24 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : integer := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_INPUT : positive := 100000000;
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CLK_FREQUENCY : positive := 50000000;
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HAS_FPU : boolean := true;
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HAS_BTC : boolean := true;
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USE_LITEDRAM : boolean := true;
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NO_BRAM : boolean := true;
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SCLK_STARTUPE2 : boolean := false;
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SPI_FLASH_OFFSET : integer := 4194304;
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SPI_FLASH_DEF_CKDV : natural := 0;
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SPI_FLASH_DEF_QUAD : boolean := true;
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LOG_LENGTH : natural := 0;
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UART_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false;
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USE_LITEETH : boolean := true;
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USE_LITESDCARD : boolean := true;
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ICACHE_NUM_LINES : natural := 64;
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NGPIO : natural := 0
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst_n : in std_ulogic;
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gsrn : in std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic;
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-- LEDs
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led5_r_n : out std_ulogic;
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led5_g_n : out std_ulogic;
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led5_b_n : out std_ulogic;
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led6_r_n : out std_ulogic;
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led6_g_n : out std_ulogic;
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led6_b_n : out std_ulogic;
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led7_r_n : out std_ulogic;
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led7_g_n : out std_ulogic;
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led7_b_n : out std_ulogic;
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led8_r_n : out std_ulogic;
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led8_g_n : out std_ulogic;
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led8_b_n : out std_ulogic;
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-- SPI
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spi_flash_cs_n : out std_ulogic;
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spi_flash_mosi : inout std_ulogic;
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spi_flash_miso : inout std_ulogic;
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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-- Ethernet
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rgmii_clocks_rx : in std_ulogic;
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rgmii_clocks_tx : out std_ulogic;
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rgmii_rst_n : out std_ulogic;
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rgmii_int_n : in std_ulogic;
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rgmii_mdc : out std_ulogic;
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rgmii_mdio : inout std_ulogic;
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rgmii_rx_ctl : in std_ulogic;
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rgmii_rx_data : in std_ulogic_vector(3 downto 0);
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rgmii_tx_ctl : out std_ulogic;
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rgmii_tx_data : out std_ulogic_vector(3 downto 0);
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-- SD card wires
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sdcard_data : inout std_ulogic_vector(3 downto 0);
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sdcard_cmd : inout std_ulogic;
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sdcard_clk : out std_ulogic;
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sdcard_cd : in std_ulogic;
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sdcard_cmd_dir : out std_ulogic;
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sdcard_dat0_dir : out std_ulogic;
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sdcard_dat13_dir : out std_ulogic;
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sdcard_vsel : out std_ulogic;
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-- PMOD ports 0 - 7
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pmod0_0 : inout std_ulogic;
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pmod0_1 : inout std_ulogic;
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pmod0_2 : inout std_ulogic;
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pmod0_3 : inout std_ulogic;
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pmod0_4 : inout std_ulogic;
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pmod0_5 : inout std_ulogic;
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pmod0_6 : inout std_ulogic;
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pmod0_7 : inout std_ulogic;
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pmod1_0 : inout std_ulogic;
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pmod1_1 : inout std_ulogic;
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pmod1_2 : inout std_ulogic;
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pmod1_3 : inout std_ulogic;
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pmod1_4 : inout std_ulogic;
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pmod1_5 : inout std_ulogic;
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pmod1_6 : inout std_ulogic;
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pmod1_7 : inout std_ulogic;
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pmod2_0 : inout std_ulogic;
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pmod2_1 : inout std_ulogic;
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pmod2_2 : inout std_ulogic;
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pmod2_3 : inout std_ulogic;
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pmod2_4 : inout std_ulogic;
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pmod2_5 : inout std_ulogic;
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pmod2_6 : inout std_ulogic;
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pmod2_7 : inout std_ulogic;
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pmod3_0 : inout std_ulogic;
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pmod3_1 : inout std_ulogic;
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pmod3_2 : inout std_ulogic;
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pmod3_3 : inout std_ulogic;
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pmod3_4 : inout std_ulogic;
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pmod3_5 : inout std_ulogic;
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pmod3_6 : inout std_ulogic;
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pmod3_7 : inout std_ulogic;
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pmod4_0 : inout std_ulogic; -- 0n
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pmod4_1 : inout std_ulogic; -- 0p
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pmod4_2 : inout std_ulogic; -- 1n
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pmod4_3 : inout std_ulogic; -- 1p
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pmod4_4 : inout std_ulogic; -- 2n
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pmod4_5 : inout std_ulogic; -- 2p
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pmod4_6 : inout std_ulogic; -- 3n
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pmod4_7 : inout std_ulogic; -- 3p
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pmod5_0 : inout std_ulogic;
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pmod5_1 : inout std_ulogic;
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pmod5_2 : inout std_ulogic;
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pmod5_3 : inout std_ulogic;
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pmod5_4 : inout std_ulogic;
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pmod5_5 : inout std_ulogic;
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pmod5_6 : inout std_ulogic;
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pmod5_7 : inout std_ulogic;
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pmod6_0 : inout std_ulogic;
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pmod6_1 : inout std_ulogic;
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pmod6_2 : inout std_ulogic;
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pmod6_3 : inout std_ulogic;
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pmod6_4 : inout std_ulogic;
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pmod6_5 : inout std_ulogic;
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pmod6_6 : inout std_ulogic;
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pmod6_7 : inout std_ulogic;
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pmod7_0 : inout std_ulogic;
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pmod7_1 : inout std_ulogic;
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pmod7_2 : inout std_ulogic;
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pmod7_3 : inout std_ulogic;
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pmod7_4 : inout std_ulogic;
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pmod7_5 : inout std_ulogic;
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pmod7_6 : inout std_ulogic;
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pmod7_7 : inout std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(14 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic_vector(0 downto 0);
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-- only the positive differential pin is instantiated
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--ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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--ddram_clk_n : out std_ulogic_vector(0 downto 0);
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- External IOs from the SoC
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signal wb_ext_io_in : wb_io_master_out;
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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signal wb_ext_is_eth : std_ulogic;
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signal wb_ext_is_sdcard : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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-- DRAM control wishbone connection
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signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteEth connection
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signal ext_irq_eth : std_ulogic;
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signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteSDCard connection
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signal ext_irq_sdcard : std_ulogic := '0';
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signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
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signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
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signal wb_sddma_in : wb_io_slave_out;
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signal wb_sddma_nr : wb_io_master_out;
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signal wb_sddma_ir : wb_io_slave_out;
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-- for conversion from non-pipelined wishbone to pipelined
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signal wb_sddma_stb_sent : std_ulogic;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_sck_ts : std_ulogic;
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signal spi_cs_n : std_ulogic;
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signal spi_sdat_o : std_ulogic_vector(3 downto 0);
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signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
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signal spi_sdat_i : std_ulogic_vector(3 downto 0);
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-- Fixup various memory sizes based on generics
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function get_bram_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return 0;
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else
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return MEMORY_SIZE;
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end if;
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end function;
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function get_payload_size return natural is
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begin
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if USE_LITEDRAM and NO_BRAM then
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return MEMORY_SIZE;
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else
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return 0;
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end if;
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end function;
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constant BRAM_SIZE : natural := get_bram_size;
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constant PAYLOAD_SIZE : natural := get_payload_size;
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COMPONENT USRMCLK
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PORT(
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USRMCLKI : IN STD_ULOGIC;
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USRMCLKTS : IN STD_ULOGIC
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);
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END COMPONENT;
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attribute syn_noprune: boolean ;
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attribute syn_noprune of USRMCLK: component is true;
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begin
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => BRAM_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_FPU => HAS_FPU,
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HAS_BTC => HAS_BTC,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 512 * 1024 * 1024,
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DRAM_INIT_SIZE => PAYLOAD_SIZE,
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HAS_SPI_FLASH => true,
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SPI_FLASH_DLINES => 4,
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SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
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SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
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SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
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LOG_LENGTH => LOG_LENGTH,
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UART0_IS_16550 => UART_IS_16550,
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HAS_UART1 => HAS_UART1,
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HAS_LITEETH => USE_LITEETH,
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HAS_SD_CARD => USE_LITESDCARD,
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ICACHE_NUM_LINES => ICACHE_NUM_LINES,
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NGPIO => NGPIO
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)
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port map (
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-- System signals
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system_clk => system_clk,
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rst => soc_rst,
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-- UART signals
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uart0_txd => uart0_txd,
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uart0_rxd => uart0_rxd,
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-- SPI signals
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spi_flash_sck => spi_sck,
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spi_flash_cs_n => spi_cs_n,
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spi_flash_sdat_o => spi_sdat_o,
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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-- External interrupts
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ext_irq_eth => ext_irq_eth,
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ext_irq_sdcard => ext_irq_sdcard,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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-- IO wishbone
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init,
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wb_ext_is_eth => wb_ext_is_eth,
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wb_ext_is_sdcard => wb_ext_is_sdcard,
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-- DMA wishbone
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wishbone_dma_in => wb_sddma_in,
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wishbone_dma_out => wb_sddma_out
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);
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-- SPI Flash
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--
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spi_flash_cs_n <= spi_cs_n;
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spi_flash_mosi <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
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spi_flash_miso <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
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spi_flash_wp_n <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
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spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
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spi_sdat_i(0) <= spi_flash_mosi;
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spi_sdat_i(1) <= spi_flash_miso;
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spi_sdat_i(2) <= spi_flash_wp_n;
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spi_sdat_i(3) <= spi_flash_hold_n;
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spi_sck_ts <= '0';
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uclk: USRMCLK port map (
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USRMCLKI => spi_sck,
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USRMCLKTS => spi_sck_ts
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);
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nodram: if not USE_LITEDRAM generate
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signal div2 : std_ulogic := '0';
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst_n and gsrn,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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process(ext_clk)
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begin
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if rising_edge(ext_clk) then
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div2 <= not div2;
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end if;
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end process;
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system_clk <= div2;
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system_clk_locked <= '1';
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led8_r_n <= '1';
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led8_g_n <= '1';
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led8_b_n <= '1';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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begin
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-- Eventually dig out the frequency from
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-- litesdram generate.py sys_clk_freq
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-- but for now, assert it's 50Mhz for ECPIX-5
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assert CLK_FREQUENCY = 50000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW,
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PLL_RESET_BITS => 18,
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SOC_RESET_BITS => 20
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked and not dram_sys_rst,
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ext_rst_in => ext_rst_n and gsrn,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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-- Generate SoC reset
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soc_rst_gen: process(system_clk)
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begin
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if ext_rst_n = '0' then
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soc_rst <= '1';
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elsif rising_edge(system_clk) then
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soc_rst <= dram_sys_rst or not system_clk_locked;
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end if;
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end process;
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 25,
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DRAM_ALINES => 15,
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DRAM_DLINES => 16,
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DRAM_CKLINES => 1,
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DRAM_PORT_WIDTH => 128,
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PAYLOAD_FILE => RAM_INIT_FILE,
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PAYLOAD_SIZE => PAYLOAD_SIZE
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => dram_sys_rst,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_ctrl_in => wb_ext_io_in,
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wb_ctrl_out => wb_dram_ctrl_out,
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wb_ctrl_is_csr => wb_ext_is_dram_csr,
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wb_ctrl_is_init => wb_ext_is_dram_init,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_clk_p => ddram_clk_p,
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-- only the positive differential pin is instantiated
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--ddram_dqs_n => ddram_dqs_n,
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--ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt
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);
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-- active-low outputs to the LED
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led8_b_n <= dram_init_done;
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led8_r_n <= not dram_init_error;
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led8_g_n <= not (dram_init_done and not dram_init_error);
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end generate;
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has_liteeth : if USE_LITEETH generate
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component liteeth_core port (
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sys_clock : in std_ulogic;
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sys_reset : in std_ulogic;
|
|
rgmii_clocks_tx : out std_ulogic;
|
|
rgmii_clocks_rx : in std_ulogic;
|
|
rgmii_rst_n : out std_ulogic;
|
|
rgmii_int_n : in std_ulogic;
|
|
rgmii_mdio : inout std_ulogic;
|
|
rgmii_mdc : out std_ulogic;
|
|
rgmii_rx_ctl : in std_ulogic;
|
|
rgmii_rx_data : in std_ulogic_vector(3 downto 0);
|
|
rgmii_tx_ctl : out std_ulogic;
|
|
rgmii_tx_data : out std_ulogic_vector(3 downto 0);
|
|
wishbone_adr : in std_ulogic_vector(29 downto 0);
|
|
wishbone_dat_w : in std_ulogic_vector(31 downto 0);
|
|
wishbone_dat_r : out std_ulogic_vector(31 downto 0);
|
|
wishbone_sel : in std_ulogic_vector(3 downto 0);
|
|
wishbone_cyc : in std_ulogic;
|
|
wishbone_stb : in std_ulogic;
|
|
wishbone_ack : out std_ulogic;
|
|
wishbone_we : in std_ulogic;
|
|
wishbone_cti : in std_ulogic_vector(2 downto 0);
|
|
wishbone_bte : in std_ulogic_vector(1 downto 0);
|
|
wishbone_err : out std_ulogic;
|
|
interrupt : out std_ulogic
|
|
);
|
|
end component;
|
|
|
|
signal wb_eth_cyc : std_ulogic;
|
|
signal wb_eth_adr : std_ulogic_vector(29 downto 0);
|
|
|
|
begin
|
|
liteeth : liteeth_core
|
|
port map(
|
|
sys_clock => system_clk,
|
|
sys_reset => soc_rst,
|
|
rgmii_clocks_tx => rgmii_clocks_tx,
|
|
rgmii_clocks_rx => rgmii_clocks_rx,
|
|
rgmii_rst_n => rgmii_rst_n,
|
|
rgmii_int_n => rgmii_int_n,
|
|
rgmii_mdio => rgmii_mdio,
|
|
rgmii_mdc => rgmii_mdc,
|
|
rgmii_rx_ctl => rgmii_rx_ctl,
|
|
rgmii_rx_data => rgmii_rx_data,
|
|
rgmii_tx_ctl => rgmii_tx_ctl,
|
|
rgmii_tx_data => rgmii_tx_data,
|
|
wishbone_adr => wb_eth_adr,
|
|
wishbone_dat_w => wb_ext_io_in.dat,
|
|
wishbone_dat_r => wb_eth_out.dat,
|
|
wishbone_sel => wb_ext_io_in.sel,
|
|
wishbone_cyc => wb_eth_cyc,
|
|
wishbone_stb => wb_ext_io_in.stb,
|
|
wishbone_ack => wb_eth_out.ack,
|
|
wishbone_we => wb_ext_io_in.we,
|
|
wishbone_cti => "000",
|
|
wishbone_bte => "00",
|
|
wishbone_err => open,
|
|
interrupt => ext_irq_eth
|
|
);
|
|
|
|
-- Gate cyc with "chip select" from soc
|
|
wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
|
|
|
|
-- Remove top address bits as liteeth decoder doesn't know about them
|
|
wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
|
|
|
|
-- LiteETH isn't pipelined
|
|
wb_eth_out.stall <= not wb_eth_out.ack;
|
|
|
|
end generate;
|
|
|
|
no_liteeth : if not USE_LITEETH generate
|
|
ext_irq_eth <= '0';
|
|
end generate;
|
|
|
|
-- SD card
|
|
-- The ECPIX-5 has a buffer/level translator chip in order to be able to
|
|
-- support 1.8V signalling to the SD card as well as 3V signalling.
|
|
-- Litesdcard doesn't currently support voltage selection, or the higher
|
|
-- data transfer rates that require the lower voltage.
|
|
has_sdcard : if USE_LITESDCARD generate
|
|
component litesdcard_core port (
|
|
clk : in std_ulogic;
|
|
rst : in std_ulogic;
|
|
irq : out std_ulogic;
|
|
-- wishbone for accessing control registers
|
|
wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
|
|
wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
|
|
wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
|
|
wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
|
|
wb_ctrl_cyc : in std_ulogic;
|
|
wb_ctrl_stb : in std_ulogic;
|
|
wb_ctrl_ack : out std_ulogic;
|
|
wb_ctrl_we : in std_ulogic;
|
|
wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
|
|
wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
|
|
wb_ctrl_err : out std_ulogic;
|
|
-- wishbone for SD card core to use for DMA
|
|
wb_dma_adr : out std_ulogic_vector(29 downto 0);
|
|
wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
|
|
wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
|
|
wb_dma_sel : out std_ulogic_vector(3 downto 0);
|
|
wb_dma_cyc : out std_ulogic;
|
|
wb_dma_stb : out std_ulogic;
|
|
wb_dma_ack : in std_ulogic;
|
|
wb_dma_we : out std_ulogic;
|
|
wb_dma_cti : out std_ulogic_vector(2 downto 0);
|
|
wb_dma_bte : out std_ulogic_vector(1 downto 0);
|
|
wb_dma_err : in std_ulogic;
|
|
-- connections to SD card
|
|
sdcard_data : inout std_ulogic_vector(3 downto 0);
|
|
sdcard_cmd : inout std_ulogic;
|
|
sdcard_clk : out std_ulogic;
|
|
sdcard_cd : in std_ulogic;
|
|
sdcard_cmd_dir : out std_ulogic;
|
|
sdcard_dat0_dir : out std_ulogic;
|
|
sdcard_dat13_dir : out std_ulogic
|
|
);
|
|
end component;
|
|
|
|
signal wb_sdcard_cyc : std_ulogic;
|
|
signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
|
|
|
|
begin
|
|
litesdcard : litesdcard_core
|
|
port map (
|
|
clk => system_clk,
|
|
rst => soc_rst,
|
|
irq => ext_irq_sdcard,
|
|
wb_ctrl_adr => wb_sdcard_adr,
|
|
wb_ctrl_dat_w => wb_ext_io_in.dat,
|
|
wb_ctrl_dat_r => wb_sdcard_out.dat,
|
|
wb_ctrl_sel => wb_ext_io_in.sel,
|
|
wb_ctrl_cyc => wb_sdcard_cyc,
|
|
wb_ctrl_stb => wb_ext_io_in.stb,
|
|
wb_ctrl_ack => wb_sdcard_out.ack,
|
|
wb_ctrl_we => wb_ext_io_in.we,
|
|
wb_ctrl_cti => "000",
|
|
wb_ctrl_bte => "00",
|
|
wb_ctrl_err => open,
|
|
wb_dma_adr => wb_sddma_nr.adr,
|
|
wb_dma_dat_w => wb_sddma_nr.dat,
|
|
wb_dma_dat_r => wb_sddma_ir.dat,
|
|
wb_dma_sel => wb_sddma_nr.sel,
|
|
wb_dma_cyc => wb_sddma_nr.cyc,
|
|
wb_dma_stb => wb_sddma_nr.stb,
|
|
wb_dma_ack => wb_sddma_ir.ack,
|
|
wb_dma_we => wb_sddma_nr.we,
|
|
wb_dma_cti => open,
|
|
wb_dma_bte => open,
|
|
wb_dma_err => '0',
|
|
sdcard_data => sdcard_data,
|
|
sdcard_cmd => sdcard_cmd,
|
|
sdcard_clk => sdcard_clk,
|
|
sdcard_cd => sdcard_cd,
|
|
sdcard_cmd_dir => sdcard_cmd_dir,
|
|
sdcard_dat0_dir => sdcard_dat0_dir,
|
|
sdcard_dat13_dir => sdcard_dat13_dir
|
|
);
|
|
|
|
-- Select 3V signalling
|
|
sdcard_vsel <= '0';
|
|
|
|
-- Gate cyc with chip select from SoC
|
|
wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
|
|
|
|
wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
|
|
|
|
wb_sdcard_out.stall <= not wb_sdcard_out.ack;
|
|
|
|
-- Convert non-pipelined DMA wishbone to pipelined by suppressing
|
|
-- non-acknowledged strobes
|
|
process(system_clk)
|
|
begin
|
|
if rising_edge(system_clk) then
|
|
wb_sddma_out <= wb_sddma_nr;
|
|
if wb_sddma_stb_sent = '1' or
|
|
(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
|
|
wb_sddma_out.stb <= '0';
|
|
end if;
|
|
if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
|
|
wb_sddma_stb_sent <= '0';
|
|
elsif wb_sddma_in.stall = '0' then
|
|
wb_sddma_stb_sent <= wb_sddma_nr.stb;
|
|
end if;
|
|
wb_sddma_ir <= wb_sddma_in;
|
|
end if;
|
|
end process;
|
|
|
|
end generate;
|
|
|
|
-- Mux WB response on the IO bus
|
|
wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
|
|
wb_sdcard_out when wb_ext_is_sdcard = '1' else
|
|
wb_dram_ctrl_out;
|
|
|
|
led5_r_n <= '1';
|
|
led5_g_n <= '1';
|
|
led5_b_n <= '1';
|
|
led6_r_n <= '1';
|
|
led6_g_n <= '1';
|
|
led6_b_n <= '1';
|
|
led7_r_n <= not soc_rst;
|
|
led7_g_n <= not system_clk_locked;
|
|
led7_b_n <= '1';
|
|
|
|
end architecture behaviour;
|