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396 lines
11 KiB
VHDL
396 lines
11 KiB
VHDL
-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2016 <kristian.skordal@wafflemail.net>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--! @brief Simple UART module.
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--! The following registers are defined:
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--! |--------------------|--------------------------------------------|
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--! | Address | Description |
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--! |--------------------|--------------------------------------------|
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--! | 0x00 | Transmit register (write-only) |
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--! | 0x08 | Receive register (read-only) |
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--! | 0x10 | Status register (read-only) |
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--! | 0x18 | Sample clock divisor register (read/write) |
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--! | 0x20 | Interrupt enable register (read/write) |
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--! |--------------------|--------------------------------------------|
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--!
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--! The status register contains the following bits:
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--! - Bit 0: receive buffer empty
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--! - Bit 1: transmit buffer empty
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--! - Bit 2: receive buffer full
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--! - Bit 3: transmit buffer full
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--!
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--! The sample clock divisor should be set according to the formula:
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--! sample_clk = (f_clk / (baudrate * 16)) - 1
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--!
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--! If the sample clock divisor register is set to 0, the sample clock
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--! is stopped.
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--!
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--! Interrupts are enabled by setting the corresponding bit in the interrupt
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--! enable register. The following bits are available:
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--! - Bit 0: data received (receive buffer not empty)
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--! - Bit 1: ready to send data (transmit buffer empty)
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entity pp_soc_uart is
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generic(
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FIFO_DEPTH : natural := 64 --! Depth of the input and output FIFOs.
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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-- UART ports:
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txd : out std_logic;
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rxd : in std_logic;
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-- Interrupt signal:
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irq : out std_logic;
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-- Wishbone ports:
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wb_adr_in : in std_logic_vector(11 downto 0);
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wb_dat_in : in std_logic_vector( 7 downto 0);
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wb_dat_out : out std_logic_vector( 7 downto 0);
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wb_we_in : in std_logic;
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_ack_out : out std_logic
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);
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end entity pp_soc_uart;
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architecture behaviour of pp_soc_uart is
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subtype bitnumber is natural range 0 to 7; --! Type representing the index of a bit.
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-- UART sample clock signals:
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signal sample_clk : std_logic;
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signal sample_clk_divisor : std_logic_vector(7 downto 0);
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signal sample_clk_counter : std_logic_vector(sample_clk_divisor'range);
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-- UART receive process signals:
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type rx_state_type is (IDLE, RECEIVE, STARTBIT, STOPBIT);
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signal rx_state : rx_state_type;
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signal rx_byte : std_logic_vector(7 downto 0);
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signal rx_current_bit : bitnumber;
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subtype rx_sample_counter_type is natural range 0 to 15;
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signal rx_sample_counter : rx_sample_counter_type;
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signal rx_sample_value : rx_sample_counter_type;
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subtype rx_sample_delay_type is natural range 0 to 7;
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signal rx_sample_delay : rx_sample_delay_type;
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-- UART transmit process signals:
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type tx_state_type is (IDLE, TRANSMIT, STOPBIT);
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signal tx_state : tx_state_type;
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signal tx_byte : std_logic_vector(7 downto 0);
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signal tx_current_bit : bitnumber;
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-- UART transmit clock:
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subtype uart_tx_counter_type is natural range 0 to 15;
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signal uart_tx_counter : uart_tx_counter_type := 0;
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signal uart_tx_clk : std_logic;
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-- Buffer signals:
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signal send_buffer_full, send_buffer_empty : std_logic;
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signal recv_buffer_full, recv_buffer_empty : std_logic;
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signal send_buffer_input, send_buffer_output : std_logic_vector(7 downto 0);
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signal recv_buffer_input, recv_buffer_output : std_logic_vector(7 downto 0);
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signal send_buffer_push, send_buffer_pop : std_logic := '0';
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signal recv_buffer_push, recv_buffer_pop : std_logic := '0';
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-- IRQ enable signals:
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signal irq_recv_enable, irq_tx_ready_enable : std_logic := '0';
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-- Wishbone signals:
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type wb_state_type is (IDLE, WRITE_ACK, READ_ACK);
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signal wb_state : wb_state_type;
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signal rxd2 : std_logic := '1';
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signal rxd3 : std_logic := '1';
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signal txd2 : std_ulogic := '1';
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begin
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irq <= (irq_recv_enable and (not recv_buffer_empty))
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or (irq_tx_ready_enable and send_buffer_empty);
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---------- UART receive ----------
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recv_buffer_input <= rx_byte;
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-- Add a few FFs on the RX input to avoid metastability issues
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process (clk) is
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begin
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if rising_edge(clk) then
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rxd3 <= rxd2;
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rxd2 <= rxd;
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end if;
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end process;
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txd <= txd2;
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uart_receive: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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rx_state <= IDLE;
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recv_buffer_push <= '0';
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else
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case rx_state is
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when IDLE =>
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if recv_buffer_push = '1' then
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recv_buffer_push <= '0';
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end if;
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if sample_clk = '1' and rxd3 = '0' then
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rx_sample_value <= rx_sample_counter;
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rx_sample_delay <= 0;
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rx_current_bit <= 0;
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rx_state <= STARTBIT;
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end if;
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when STARTBIT =>
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if sample_clk = '1' then
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if rx_sample_delay = 7 then
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rx_state <= RECEIVE;
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rx_sample_value <= rx_sample_counter;
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rx_sample_delay <= 0;
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else
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rx_sample_delay <= rx_sample_delay + 1;
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end if;
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end if;
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when RECEIVE =>
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if sample_clk = '1' and rx_sample_counter = rx_sample_value then
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if rx_current_bit /= 7 then
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rx_byte(rx_current_bit) <= rxd3;
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rx_current_bit <= rx_current_bit + 1;
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else
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rx_byte(rx_current_bit) <= rxd3;
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rx_state <= STOPBIT;
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end if;
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end if;
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when STOPBIT =>
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if sample_clk = '1' and rx_sample_counter = rx_sample_value then
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rx_state <= IDLE;
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if recv_buffer_full = '0' then
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recv_buffer_push <= '1';
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end if;
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end if;
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end case;
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end if;
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end if;
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end process uart_receive;
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sample_counter: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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rx_sample_counter <= 0;
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elsif sample_clk = '1' then
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if rx_sample_counter = 15 then
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rx_sample_counter <= 0;
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else
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rx_sample_counter <= rx_sample_counter + 1;
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end if;
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end if;
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end if;
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end process sample_counter;
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---------- UART transmit ----------
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tx_byte <= send_buffer_output;
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uart_transmit: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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txd2 <= '1';
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tx_state <= IDLE;
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send_buffer_pop <= '0';
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tx_current_bit <= 0;
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else
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case tx_state is
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when IDLE =>
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if send_buffer_empty = '0' and uart_tx_clk = '1' then
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txd2 <= '0';
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send_buffer_pop <= '1';
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tx_current_bit <= 0;
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tx_state <= TRANSMIT;
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elsif uart_tx_clk = '1' then
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txd2 <= '1';
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end if;
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when TRANSMIT =>
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if send_buffer_pop = '1' then
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send_buffer_pop <= '0';
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elsif uart_tx_clk = '1' and tx_current_bit = 7 then
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txd2 <= tx_byte(tx_current_bit);
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tx_state <= STOPBIT;
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elsif uart_tx_clk = '1' then
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txd2 <= tx_byte(tx_current_bit);
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tx_current_bit <= tx_current_bit + 1;
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end if;
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when STOPBIT =>
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if uart_tx_clk = '1' then
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txd2 <= '1';
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tx_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process uart_transmit;
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uart_tx_clock_generator: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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uart_tx_counter <= 0;
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uart_tx_clk <= '0';
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else
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if sample_clk = '1' then
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if uart_tx_counter = 15 then
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uart_tx_counter <= 0;
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uart_tx_clk <= '1';
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else
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uart_tx_counter <= uart_tx_counter + 1;
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uart_tx_clk <= '0';
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end if;
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else
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uart_tx_clk <= '0';
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end if;
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end if;
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end if;
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end process uart_tx_clock_generator;
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---------- Sample clock generator ----------
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sample_clock_generator: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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sample_clk_counter <= (others => '0');
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sample_clk <= '0';
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else
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if sample_clk_divisor /= x"00" then
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if sample_clk_counter = sample_clk_divisor then
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sample_clk_counter <= (others => '0');
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sample_clk <= '1';
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else
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sample_clk_counter <= std_logic_vector(unsigned(sample_clk_counter) + 1);
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sample_clk <= '0';
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end if;
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end if;
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end if;
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end if;
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end process sample_clock_generator;
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---------- Data Buffers ----------
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send_buffer: entity work.pp_fifo
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generic map(
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DEPTH => FIFO_DEPTH,
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WIDTH => 8
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) port map(
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clk => clk,
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reset => reset,
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full => send_buffer_full,
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empty => send_buffer_empty,
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data_in => send_buffer_input,
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data_out => send_buffer_output,
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push => send_buffer_push,
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pop => send_buffer_pop
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);
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recv_buffer: entity work.pp_fifo
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generic map(
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DEPTH => FIFO_DEPTH,
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WIDTH => 8
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) port map(
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clk => clk,
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reset => reset,
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full => recv_buffer_full,
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empty => recv_buffer_empty,
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data_in => recv_buffer_input,
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data_out => recv_buffer_output,
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push => recv_buffer_push,
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pop => recv_buffer_pop
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);
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---------- Wishbone Interface ----------
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wishbone: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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wb_ack_out <= '0';
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wb_state <= IDLE;
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send_buffer_push <= '0';
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recv_buffer_pop <= '0';
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sample_clk_divisor <= (others => '0');
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irq_recv_enable <= '0';
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irq_tx_ready_enable <= '0';
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else
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case wb_state is
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when IDLE =>
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if wb_cyc_in = '1' and wb_stb_in = '1' then
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if wb_we_in = '1' then -- Write to register
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if wb_adr_in = x"000" then
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send_buffer_input <= wb_dat_in;
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send_buffer_push <= '1';
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elsif wb_adr_in = x"018" then
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sample_clk_divisor <= wb_dat_in;
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elsif wb_adr_in = x"020" then
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irq_recv_enable <= wb_dat_in(0);
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irq_tx_ready_enable <= wb_dat_in(1);
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end if;
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-- Invalid writes are acked and ignored.
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wb_ack_out <= '1';
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wb_state <= WRITE_ACK;
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else -- Read from register
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if wb_adr_in = x"008" then
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recv_buffer_pop <= '1';
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elsif wb_adr_in = x"010" then
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wb_dat_out <= x"0" & send_buffer_full & recv_buffer_full &
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send_buffer_empty & recv_buffer_empty;
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wb_ack_out <= '1';
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elsif wb_adr_in = x"018" then
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wb_dat_out <= sample_clk_divisor;
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wb_ack_out <= '1';
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elsif wb_adr_in = x"020" then
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wb_dat_out <= (0 => irq_recv_enable,
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1 => irq_tx_ready_enable,
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others => '0');
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wb_ack_out <= '1';
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else
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wb_dat_out <= (others => '0');
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wb_ack_out <= '1';
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end if;
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wb_state <= READ_ACK;
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end if;
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end if;
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when WRITE_ACK =>
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send_buffer_push <= '0';
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if wb_stb_in = '0' then
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wb_ack_out <= '0';
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wb_state <= IDLE;
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end if;
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when READ_ACK =>
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if recv_buffer_pop = '1' then
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recv_buffer_pop <= '0';
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else
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wb_dat_out <= recv_buffer_output;
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wb_ack_out <= '1';
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end if;
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if wb_stb_in = '0' then
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wb_ack_out <= '0';
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wb_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process wishbone;
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end architecture behaviour;
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