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83 lines
2.4 KiB
VHDL
83 lines
2.4 KiB
VHDL
-- Single port Block RAM with one cycle output buffer
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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entity main_bram is
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generic(
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WIDTH : natural := 64;
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HEIGHT_BITS : natural := 1024;
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MEMORY_SIZE : natural := 65536;
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RAM_INIT_FILE : string
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);
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port(
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clk : in std_logic;
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addr : in std_logic_vector(HEIGHT_BITS - 1 downto 0) ;
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din : in std_logic_vector(WIDTH-1 downto 0);
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dout : out std_logic_vector(WIDTH-1 downto 0);
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sel : in std_logic_vector((WIDTH/8)-1 downto 0);
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re : in std_ulogic;
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we : in std_ulogic
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);
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end entity main_bram;
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architecture behaviour of main_bram is
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constant WIDTH_BYTES : natural := WIDTH / 8;
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-- RAM type definition
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type ram_t is array(0 to (MEMORY_SIZE / WIDTH_BYTES) - 1) of std_logic_vector(WIDTH-1 downto 0);
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-- RAM loading
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impure function init_ram(name : STRING) return ram_t is
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file ram_file : text open read_mode is name;
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variable ram_line : line;
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variable temp_word : std_logic_vector(WIDTH-1 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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begin
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for i in 0 to (MEMORY_SIZE / WIDTH_BYTES) - 1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i) := temp_word;
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end loop;
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return temp_ram;
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end function;
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-- RAM instance
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signal memory : ram_t := init_ram(RAM_INIT_FILE);
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attribute ram_style : string;
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attribute ram_style of memory : signal is "block";
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attribute ram_decomp : string;
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attribute ram_decomp of memory : signal is "power";
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-- Others
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signal obuf : std_logic_vector(WIDTH-1 downto 0);
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begin
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-- Actual RAM template
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memory_0: process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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for i in 0 to 7 loop
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if sel(i) = '1' then
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memory(to_integer(unsigned(addr)))((i + 1) * 8 - 1 downto i * 8) <=
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din((i + 1) * 8 - 1 downto i * 8);
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end if;
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end loop;
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end if;
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if re = '1' then
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obuf <= memory(to_integer(unsigned(addr)));
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end if;
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dout <= obuf;
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end if;
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end process;
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end architecture behaviour;
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