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54 lines
1.6 KiB
VHDL
54 lines
1.6 KiB
VHDL
-- Random number generator for Microwatt
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-- Based on https://pdfs.semanticscholar.org/83ac/9e9c1bb3dad5180654984604c8d5d8137412.pdf
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-- "High Speed True Random Number Generators in Xilinx FPGAs"
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-- by Catalin Baetoniu, Xilinx Inc.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity random is
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port (
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clk : in std_ulogic;
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data : out std_ulogic_vector(63 downto 0);
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raw : out std_ulogic_vector(63 downto 0);
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err : out std_ulogic
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);
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end entity random;
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architecture behaviour of random is
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signal ringosc : std_ulogic_vector(63 downto 0);
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signal ro_reg : std_ulogic_vector(63 downto 0);
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signal lhca : std_ulogic_vector(63 downto 0);
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constant lhca_diag : std_ulogic_vector(63 downto 0) := x"fffffffffffffffb";
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begin
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random_osc : process(all)
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begin
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-- chaotic set of ring oscillators
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ringosc(0) <= ringosc(63) xor ringosc(0) xor ringosc(1);
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for i in 1 to 62 loop
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ringosc(i) <= ringosc(i-1) xor ringosc(i) xor ringosc(i+1);
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end loop;
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ringosc(63) <= not (ringosc(62) xor ringosc(63) xor ringosc(0));
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end process;
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lhca_update : process(clk)
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begin
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if rising_edge(clk) then
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ro_reg <= ringosc;
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raw <= ro_reg;
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-- linear hybrid cellular automaton
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-- used to even out the statistics of the ring oscillators
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lhca <= ('0' & lhca(63 downto 1)) xor (lhca and lhca_diag) xor
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(lhca(62 downto 0) & '0') xor ro_reg;
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end if;
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end process;
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data <= lhca;
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err <= '0';
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end behaviour;
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