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130 lines
3.7 KiB
VHDL
130 lines
3.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity soc_reset_tb is
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end soc_reset_tb;
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architecture behave of soc_reset_tb is
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signal ext_clk : std_ulogic;
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signal pll_clk : std_ulogic;
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signal pll_locked_in : std_ulogic;
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signal ext_rst_in : std_ulogic;
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signal pll_rst_out : std_ulogic;
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signal rst_out : std_ulogic;
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constant clk_period : time := 10 ns;
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type test_vector is record
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pll_locked_in : std_ulogic;
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ext_rst_in : std_ulogic;
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pll_rst_out : std_ulogic;
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rst_out : std_ulogic;
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end record;
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type test_vector_array is array (natural range <>) of test_vector;
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constant test_vectors : test_vector_array := (
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-- PLL not locked, reset button not pressed
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('0', '1', '1', '1'),
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('0', '1', '1', '1'),
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('0', '1', '1', '1'),
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('0', '1', '1', '1'),
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('0', '1', '1', '1'),
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('0', '1', '1', '1'),
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-- Reset is removed from the PLL
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('0', '1', '0', '1'),
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('0', '1', '0', '1'),
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('0', '1', '0', '1'),
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-- At some point PLL comes out of reset
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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-- Finally SOC comes out of reset
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('1', '1', '0', '0'),
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('1', '1', '0', '0'),
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-- PLL locked, reset button pressed
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('1', '0', '0', '0'),
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('1', '0', '0', '0'),
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('1', '0', '0', '0'),
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('1', '0', '1', '1'),
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-- PLL locked, reset button released
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('1', '1', '1', '1'),
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('1', '1', '1', '1'),
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('1', '1', '1', '1'),
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('1', '1', '1', '1'),
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('1', '1', '1', '1'),
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('1', '1', '1', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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('1', '1', '0', '1'),
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-- Finally SOC comes out of reset
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('1', '1', '0', '0')
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);
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begin
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soc_reset_0: entity work.soc_reset
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generic map (
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PLL_RESET_BITS => 2,
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SOC_RESET_BITS => 2,
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RESET_LOW => true
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)
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port map (
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ext_clk => ext_clk,
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pll_clk => pll_clk,
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pll_locked_in => pll_locked_in,
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ext_rst_in => ext_rst_in,
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pll_rst_out => pll_rst_out,
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rst_out => rst_out
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);
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clock: process
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begin
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ext_clk <= '0';
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pll_clk <= '0';
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wait for clk_period/2;
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ext_clk <= '1';
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pll_clk <= '1';
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wait for clk_period/2;
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end process clock;
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stim: process
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variable tv : test_vector;
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begin
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-- skew us a bit
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wait for clk_period/4;
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for i in test_vectors'range loop
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tv := test_vectors(i);
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pll_locked_in <= tv.pll_locked_in;
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ext_rst_in <= tv.ext_rst_in;
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report " ** STEP " & integer'image(i);
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report "pll_locked_in " & std_ulogic'image(pll_locked_in);
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report "ext_rst_in " & std_ulogic'image(ext_rst_in);
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report "pll_rst_out " & std_ulogic'image(pll_rst_out);
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report "rst_out" & std_ulogic'image(rst_out);
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assert tv.pll_rst_out = pll_rst_out report
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"pll_rst_out bad exp=" & std_ulogic'image(tv.pll_rst_out) &
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" got=" & std_ulogic'image(pll_rst_out);
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assert tv.rst_out = rst_out report
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"rst_out bad exp=" & std_ulogic'image(tv.rst_out) &
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" got=" & std_ulogic'image(rst_out);
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wait for clk_period;
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end loop;
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wait for clk_period;
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std.env.finish;
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end process;
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end behave;
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