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8901e84d8d
Parameters are based on https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py and litex-boards orangecrab.py rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here. Generated with litedram and litex 62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.") add2746a ("tools/litex_cli: Rename wb to bus.") Signed-off-by: Matt Johnston <matt@codeconstruct.com.au> |
3 years ago | |
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sdram_init | 3 years ago | |
acorn-cle-215.yml | 3 years ago | |
arty.yml | 3 years ago | |
dram-init-mem.vhdl | 3 years ago | |
generate.py | 3 years ago | |
genesys2.yml | 3 years ago | |
nexys-video.yml | 3 years ago | |
no-init-mem.vhdl | ||
orangecrab-85-0.2.yml | 3 years ago | |
sim.yml | 3 years ago | |
wukong-v2.yml | 3 years ago |