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540 lines
19 KiB
VHDL
540 lines
19 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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generic (
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-- Non-zero to enable log data collection
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LOG_LENGTH : natural := 0
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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l_in : in Execute1ToLoadstore1Type;
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e_out : out Loadstore1ToExecute1Type;
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l_out : out Loadstore1ToWritebackType;
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d_out : out Loadstore1ToDcacheType;
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d_in : in DcacheToLoadstore1Type;
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m_out : out Loadstore1ToMmuType;
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m_in : in MmuToLoadstore1Type;
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dc_stall : in std_ulogic;
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log_out : out std_ulogic_vector(9 downto 0)
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);
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end loadstore1;
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-- Note, we don't currently use the stall output from the dcache because
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-- we know it can take two requests without stalling when idle, we are
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-- its only user, and we know it never stalls when idle.
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architecture behave of loadstore1 is
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-- State machine for unaligned loads/stores
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type state_t is (IDLE, -- ready for instruction
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SECOND_REQ, -- send 2nd request of unaligned xfer
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ACK_WAIT, -- waiting for ack from dcache
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LD_UPDATE, -- writing rA with computed addr on load
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MMU_LOOKUP, -- waiting for MMU to look up translation
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TLBIE_WAIT, -- waiting for MMU to finish doing a tlbie
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SPR_CMPLT -- complete a mf/tspr operation
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);
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type reg_stage_t is record
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-- latch most of the input request
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load : std_ulogic;
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tlbie : std_ulogic;
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dcbz : std_ulogic;
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mfspr : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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store_data : std_ulogic_vector(63 downto 0);
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load_data : std_ulogic_vector(63 downto 0);
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write_reg : gpr_index_t;
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length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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update_reg : gpr_index_t;
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xerc : xer_common_t;
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reserve : std_ulogic;
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rc : std_ulogic;
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nc : std_ulogic; -- non-cacheable access
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virt_mode : std_ulogic;
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priv_mode : std_ulogic;
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state : state_t;
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dwords_done : std_ulogic;
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last_dword : std_ulogic;
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first_bytes : std_ulogic_vector(7 downto 0);
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second_bytes : std_ulogic_vector(7 downto 0);
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dar : std_ulogic_vector(63 downto 0);
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dsisr : std_ulogic_vector(31 downto 0);
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instr_fault : std_ulogic;
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sprval : std_ulogic_vector(63 downto 0);
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end record;
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type byte_sel_t is array(0 to 7) of std_ulogic;
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subtype byte_trim_t is std_ulogic_vector(1 downto 0);
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type trim_ctl_t is array(0 to 7) of byte_trim_t;
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signal r, rin : reg_stage_t;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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-- Generate byte enables from sizes
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function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
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begin
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case length is
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when "0001" =>
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return "00000001";
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when "0010" =>
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return "00000011";
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when "0100" =>
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return "00001111";
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when "1000" =>
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return "11111111";
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when others =>
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return "00000000";
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end case;
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end function length_to_sel;
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-- Calculate byte enables
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-- This returns 16 bits, giving the select signals for two transfers,
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-- to account for unaligned loads or stores
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function xfer_data_sel(size : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(2 downto 0))
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return std_ulogic_vector is
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variable longsel : std_ulogic_vector(15 downto 0);
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begin
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longsel := "00000000" & length_to_sel(size);
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return std_ulogic_vector(shift_left(unsigned(longsel),
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to_integer(unsigned(address))));
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end function xfer_data_sel;
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begin
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-- Calculate the address in the first cycle
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lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
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loadstore1_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r.state <= IDLE;
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else
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r <= rin;
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end if;
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end if;
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end process;
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loadstore1_1: process(all)
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variable v : reg_stage_t;
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variable brev_lenm1 : unsigned(2 downto 0);
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variable byte_offset : unsigned(2 downto 0);
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variable j : integer;
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variable k : unsigned(2 downto 0);
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variable kk : unsigned(3 downto 0);
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variable long_sel : std_ulogic_vector(15 downto 0);
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variable byte_sel : std_ulogic_vector(7 downto 0);
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variable req : std_ulogic;
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variable busy : std_ulogic;
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variable addr : std_ulogic_vector(63 downto 0);
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variable wdata : std_ulogic_vector(63 downto 0);
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variable write_enable : std_ulogic;
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variable do_update : std_ulogic;
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variable done : std_ulogic;
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variable data_permuted : std_ulogic_vector(63 downto 0);
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variable data_trimmed : std_ulogic_vector(63 downto 0);
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variable use_second : byte_sel_t;
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variable trim_ctl : trim_ctl_t;
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variable negative : std_ulogic;
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variable sprn : std_ulogic_vector(9 downto 0);
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variable exception : std_ulogic;
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variable next_addr : std_ulogic_vector(63 downto 0);
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variable mmureq : std_ulogic;
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variable dsisr : std_ulogic_vector(31 downto 0);
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variable mmu_mtspr : std_ulogic;
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variable itlb_fault : std_ulogic;
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begin
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v := r;
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req := '0';
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byte_sel := (others => '0');
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addr := lsu_sum;
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v.mfspr := '0';
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mmu_mtspr := '0';
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itlb_fault := '0';
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sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
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dsisr := (others => '0');
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mmureq := '0';
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write_enable := '0';
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do_update := '0';
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-- load data formatting
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byte_offset := unsigned(r.addr(2 downto 0));
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brev_lenm1 := "000";
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if r.byte_reverse = '1' then
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brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
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end if;
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-- shift and byte-reverse data bytes
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for i in 0 to 7 loop
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kk := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
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use_second(i) := kk(3);
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j := to_integer(kk(2 downto 0)) * 8;
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data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
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end loop;
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-- Work out the sign bit for sign extension.
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-- Assumes we are not doing both sign extension and byte reversal,
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-- in that for unaligned loads crossing two dwords we end up
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-- using a bit from the second dword, whereas for a byte-reversed
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-- (i.e. big-endian) load the sign bit would be in the first dword.
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negative := (r.length(3) and data_permuted(63)) or
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(r.length(2) and data_permuted(31)) or
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(r.length(1) and data_permuted(15)) or
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(r.length(0) and data_permuted(7));
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-- trim and sign-extend
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for i in 0 to 7 loop
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if i < to_integer(unsigned(r.length)) then
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if r.dwords_done = '1' then
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trim_ctl(i) := '1' & not use_second(i);
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else
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trim_ctl(i) := "10";
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end if;
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else
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trim_ctl(i) := '0' & (negative and r.sign_extend);
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end if;
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case trim_ctl(i) is
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when "11" =>
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data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
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when "10" =>
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data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
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when "01" =>
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data_trimmed(i * 8 + 7 downto i * 8) := x"FF";
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when others =>
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data_trimmed(i * 8 + 7 downto i * 8) := x"00";
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end case;
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end loop;
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-- compute (addr + 8) & ~7 for the second doubleword when unaligned
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next_addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
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done := '0';
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exception := '0';
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case r.state is
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when IDLE =>
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when SECOND_REQ =>
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addr := next_addr;
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byte_sel := r.second_bytes;
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req := '1';
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v.state := ACK_WAIT;
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v.last_dword := '0';
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when ACK_WAIT =>
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if d_in.valid = '1' then
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if d_in.error = '1' then
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-- dcache will discard the second request if it
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-- gets an error on the 1st of two requests
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if r.dwords_done = '1' then
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addr := next_addr;
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else
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addr := r.addr;
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end if;
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if d_in.cache_paradox = '1' then
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-- signal an interrupt straight away
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exception := '1';
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dsisr(63 - 38) := not r.load;
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-- XXX there is no architected bit for this
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dsisr(63 - 35) := d_in.cache_paradox;
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v.state := IDLE;
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else
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-- Look up the translation for TLB miss
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-- and also for permission error and RC error
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-- in case the PTE has been updated.
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mmureq := '1';
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v.state := MMU_LOOKUP;
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end if;
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else
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if r.last_dword = '0' then
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v.dwords_done := '1';
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v.last_dword := '1';
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if r.load = '1' then
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v.load_data := data_permuted;
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end if;
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else
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write_enable := r.load;
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if r.load = '1' and r.update = '1' then
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-- loads with rA update need an extra cycle
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v.state := LD_UPDATE;
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else
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-- stores write back rA update in this cycle
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do_update := r.update;
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done := '1';
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v.state := IDLE;
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end if;
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end if;
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end if;
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end if;
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when MMU_LOOKUP =>
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if r.dwords_done = '1' then
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addr := next_addr;
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byte_sel := r.second_bytes;
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else
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addr := r.addr;
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byte_sel := r.first_bytes;
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end if;
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if m_in.done = '1' then
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if m_in.invalid = '0' and m_in.perm_error = '0' and m_in.rc_error = '0' and
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m_in.badtree = '0' and m_in.segerr = '0' then
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if r.instr_fault = '0' then
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-- retry the request now that the MMU has installed a TLB entry
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req := '1';
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if r.last_dword = '0' then
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v.state := SECOND_REQ;
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else
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v.state := ACK_WAIT;
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end if;
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else
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-- nothing to do, the icache retries automatically
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done := '1';
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v.state := IDLE;
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end if;
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else
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exception := '1';
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dsisr(63 - 33) := m_in.invalid;
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dsisr(63 - 36) := m_in.perm_error;
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dsisr(63 - 38) := not r.load;
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dsisr(63 - 44) := m_in.badtree;
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dsisr(63 - 45) := m_in.rc_error;
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v.state := IDLE;
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end if;
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end if;
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when TLBIE_WAIT =>
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if m_in.done = '1' then
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-- tlbie is finished
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done := '1';
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v.state := IDLE;
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end if;
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when LD_UPDATE =>
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do_update := '1';
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v.state := IDLE;
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done := '1';
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when SPR_CMPLT =>
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done := '1';
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v.state := IDLE;
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end case;
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busy := '1';
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if r.state = IDLE or done = '1' then
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busy := '0';
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end if;
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-- Note that l_in.valid is gated with busy inside execute1
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if l_in.valid = '1' then
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v.addr := lsu_sum;
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v.load := '0';
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v.dcbz := '0';
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v.tlbie := '0';
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v.instr_fault := '0';
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v.dwords_done := '0';
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v.last_dword := '1';
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.update_reg := l_in.update_reg;
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v.xerc := l_in.xerc;
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v.reserve := l_in.reserve;
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v.rc := l_in.rc;
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v.nc := l_in.ci;
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v.virt_mode := l_in.virt_mode;
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v.priv_mode := l_in.priv_mode;
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc------- for a real-mode access.
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if lsu_sum(31 downto 28) = "1100" and l_in.virt_mode = '0' then
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v.nc := '1';
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end if;
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-- Do length_to_sel and work out if we are doing 2 dwords
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long_sel := xfer_data_sel(l_in.length, v.addr(2 downto 0));
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byte_sel := long_sel(7 downto 0);
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v.first_bytes := byte_sel;
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v.second_bytes := long_sel(15 downto 8);
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-- Do byte reversing and rotating for stores in the first cycle
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byte_offset := unsigned(lsu_sum(2 downto 0));
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brev_lenm1 := "000";
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if l_in.byte_reverse = '1' then
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brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
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end if;
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for i in 0 to 7 loop
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k := (to_unsigned(i, 3) xor brev_lenm1) + byte_offset;
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j := to_integer(k) * 8;
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v.store_data(j + 7 downto j) := l_in.data(i * 8 + 7 downto i * 8);
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end loop;
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case l_in.op is
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when OP_STORE =>
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req := '1';
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when OP_LOAD =>
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req := '1';
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v.load := '1';
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when OP_DCBZ =>
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req := '1';
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v.dcbz := '1';
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when OP_TLBIE =>
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mmureq := '1';
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v.tlbie := '1';
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v.state := TLBIE_WAIT;
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when OP_MFSPR =>
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v.mfspr := '1';
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-- partial decode on SPR number should be adequate given
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-- the restricted set that get sent down this path
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if sprn(9) = '0' and sprn(5) = '0' then
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if sprn(0) = '0' then
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v.sprval := x"00000000" & r.dsisr;
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else
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v.sprval := r.dar;
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end if;
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else
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-- reading one of the SPRs in the MMU
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v.sprval := m_in.sprval;
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end if;
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v.state := SPR_CMPLT;
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when OP_MTSPR =>
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if sprn(9) = '0' and sprn(5) = '0' then
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if sprn(0) = '0' then
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v.dsisr := l_in.data(31 downto 0);
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else
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v.dar := l_in.data;
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end if;
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v.state := SPR_CMPLT;
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else
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-- writing one of the SPRs in the MMU
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mmu_mtspr := '1';
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v.state := TLBIE_WAIT;
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end if;
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when OP_FETCH_FAILED =>
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-- send it to the MMU to do the radix walk
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addr := l_in.nia;
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v.addr := l_in.nia;
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v.instr_fault := '1';
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mmureq := '1';
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v.state := MMU_LOOKUP;
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when others =>
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assert false report "unknown op sent to loadstore1";
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end case;
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if req = '1' then
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if long_sel(15 downto 8) = "00000000" then
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v.state := ACK_WAIT;
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else
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v.state := SECOND_REQ;
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end if;
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end if;
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end if;
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-- Update outputs to dcache
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d_out.valid <= req;
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d_out.load <= v.load;
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d_out.dcbz <= v.dcbz;
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d_out.nc <= v.nc;
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d_out.reserve <= v.reserve;
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d_out.addr <= addr;
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d_out.data <= v.store_data;
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d_out.byte_sel <= byte_sel;
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d_out.virt_mode <= v.virt_mode;
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d_out.priv_mode <= v.priv_mode;
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-- Update outputs to MMU
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m_out.valid <= mmureq;
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m_out.iside <= v.instr_fault;
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m_out.load <= r.load;
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m_out.priv <= r.priv_mode;
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m_out.tlbie <= v.tlbie;
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m_out.mtspr <= mmu_mtspr;
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m_out.sprn <= sprn;
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m_out.addr <= addr;
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m_out.slbia <= l_in.insn(7);
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m_out.rs <= l_in.data;
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-- Update outputs to writeback
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-- Multiplex either cache data to the destination GPR or
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-- the address for the rA update.
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l_out.valid <= done;
|
|
if r.mfspr = '1' then
|
|
l_out.write_enable <= '1';
|
|
l_out.write_reg <= r.write_reg;
|
|
l_out.write_data <= r.sprval;
|
|
elsif do_update = '1' then
|
|
l_out.write_enable <= '1';
|
|
l_out.write_reg <= r.update_reg;
|
|
l_out.write_data <= r.addr;
|
|
else
|
|
l_out.write_enable <= write_enable;
|
|
l_out.write_reg <= r.write_reg;
|
|
l_out.write_data <= data_trimmed;
|
|
end if;
|
|
l_out.xerc <= r.xerc;
|
|
l_out.rc <= r.rc and done;
|
|
l_out.store_done <= d_in.store_done;
|
|
|
|
-- update exception info back to execute1
|
|
e_out.busy <= busy;
|
|
e_out.exception <= exception;
|
|
e_out.instr_fault <= r.instr_fault;
|
|
e_out.invalid <= m_in.invalid;
|
|
e_out.badtree <= m_in.badtree;
|
|
e_out.perm_error <= m_in.perm_error;
|
|
e_out.rc_error <= m_in.rc_error;
|
|
e_out.segment_fault <= m_in.segerr;
|
|
if exception = '1' and r.instr_fault = '0' then
|
|
v.dar := addr;
|
|
if m_in.segerr = '0' then
|
|
v.dsisr := dsisr;
|
|
end if;
|
|
end if;
|
|
|
|
-- Update registers
|
|
rin <= v;
|
|
|
|
end process;
|
|
|
|
l1_log: if LOG_LENGTH > 0 generate
|
|
signal log_data : std_ulogic_vector(9 downto 0);
|
|
begin
|
|
ls1_log: process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
log_data <= e_out.busy &
|
|
e_out.exception &
|
|
l_out.valid &
|
|
m_out.valid &
|
|
d_out.valid &
|
|
m_in.done &
|
|
r.dwords_done &
|
|
std_ulogic_vector(to_unsigned(state_t'pos(r.state), 3));
|
|
end if;
|
|
end process;
|
|
log_out <= log_data;
|
|
end generate;
|
|
|
|
end;
|