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Paul Mackerras d0f319290f Restore debug access to SPRs ... This provides access to the SPRs via the JTAG DMI interface. For now they are still accessed as if they were GPR/FPRs using the same numbering as before (GPRs at 0 - 0x1f, SPRs at 0x20 - 0x2d, FPRs at 0x40 - 0x5f). For XER, debug reads now report the full value, not just the bits that were previously stored in the register file. The "slow" SPR mux is not used for debug reads. Decode2 determines on each cycle whether a debug SPR access will happen next cycle, based on whether there is a request and whether the current instruction accesses the SPR RAM. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		2 years ago
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fmt_log	decode: Add a facility field to the instruction decode tables	3 years ago
mw_debug	Restore debug access to SPRs	2 years ago
bin2hex.py	bin2hex: Make sure to generate little endian files	4 years ago
dependencies.py	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	4 years ago
gen_icache_tb.py	icache_tb: Improve test and include test file	5 years ago
run_test.sh	Move XER low bits out of register file	2 years ago
run_test_console.sh	Add test cases for new exceptions and supervisor state	4 years ago
test_micropython.py	Update micropython	4 years ago
test_micropython_long.py	Update micropython	4 years ago
test_micropython_verilator.py	makefile: Add some verilator micropython tests	3 years ago
test_micropython_verilator_long.py	makefile: Add some verilator micropython tests	3 years ago
vhdltags	Add VHDL TAGS	4 years ago