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Paul Mackerras
d0f319290f
This provides access to the SPRs via the JTAG DMI interface. For now they are still accessed as if they were GPR/FPRs using the same numbering as before (GPRs at 0 - 0x1f, SPRs at 0x20 - 0x2d, FPRs at 0x40 - 0x5f). For XER, debug reads now report the full value, not just the bits that were previously stored in the register file. The "slow" SPR mux is not used for debug reads. Decode2 determines on each cycle whether a debug SPR access will happen next cycle, based on whether there is a request and whether the current instruction accesses the SPR RAM. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
2 years ago | |
|---|---|---|
| .. | ||
| fmt_log | 4 years ago | |
| mw_debug | 2 years ago | |
| bin2hex.py | ||
| dependencies.py | 5 years ago | |
| gen_icache_tb.py | ||
| run_test.sh | 3 years ago | |
| run_test_console.sh | ||
| test_micropython.py | ||
| test_micropython_long.py | ||
| test_micropython_verilator.py | 3 years ago | |
| test_micropython_verilator_long.py | 3 years ago | |
| vhdltags | ||