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584 lines
21 KiB
VHDL
584 lines
21 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.helpers.all;
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use work.insn_helpers.all;
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entity decode2 is
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generic (
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EX1_BYPASS : boolean := true;
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HAS_FPU : boolean := true;
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-- Non-zero to enable log data collection
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LOG_LENGTH : natural := 0
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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complete_in : in instr_tag_t;
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busy_in : in std_ulogic;
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stall_out : out std_ulogic;
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stopped_out : out std_ulogic;
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flush_in: in std_ulogic;
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d_in : in Decode1ToDecode2Type;
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e_out : out Decode2ToExecute1Type;
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r_in : in RegisterFileToDecode2Type;
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r_out : out Decode2ToRegisterFileType;
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c_in : in CrFileToDecode2Type;
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c_out : out Decode2ToCrFileType;
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execute_bypass : in bypass_data_t;
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execute_cr_bypass : in cr_bypass_data_t;
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log_out : out std_ulogic_vector(9 downto 0)
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);
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end entity decode2;
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architecture behaviour of decode2 is
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type reg_type is record
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e : Decode2ToExecute1Type;
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repeat : std_ulogic;
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end record;
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signal r, rin : reg_type;
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signal deferred : std_ulogic;
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type decode_input_reg_t is record
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reg_valid : std_ulogic;
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reg : gspr_index_t;
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data : std_ulogic_vector(63 downto 0);
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end record;
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type decode_output_reg_t is record
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reg_valid : std_ulogic;
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reg : gspr_index_t;
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end record;
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function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0);
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ispr : gspr_index_t;
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instr_addr : std_ulogic_vector(63 downto 0))
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return decode_input_reg_t is
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begin
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if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
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return ('1', gpr_to_gspr(insn_ra(insn_in)), reg_data);
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elsif t = SPR then
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-- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
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-- If it's all 0, we don't treat it as a dependency as slow SPRs
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-- operations are single issue.
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--
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assert is_fast_spr(ispr) = '1' or ispr = "0000000"
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report "Decode A says SPR but ISPR is invalid:" &
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to_hstring(ispr) severity failure;
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return (is_fast_spr(ispr), ispr, reg_data);
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elsif t = CIA then
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return ('0', (others => '0'), instr_addr);
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elsif HAS_FPU and t = FRA then
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return ('1', fpr_to_gspr(insn_fra(insn_in)), reg_data);
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else
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return ('0', (others => '0'), (others => '0'));
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end if;
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end;
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function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0);
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ispr : gspr_index_t) return decode_input_reg_t is
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variable ret : decode_input_reg_t;
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begin
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case t is
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when RB =>
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ret := ('1', gpr_to_gspr(insn_rb(insn_in)), reg_data);
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when FRB =>
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if HAS_FPU then
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ret := ('1', fpr_to_gspr(insn_frb(insn_in)), reg_data);
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else
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ret := ('0', (others => '0'), (others => '0'));
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end if;
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when CONST_UI =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
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when CONST_SI =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
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when CONST_SI_HI =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
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when CONST_UI_HI =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
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when CONST_LI =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
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when CONST_BD =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
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when CONST_DS =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
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when CONST_DQ =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dq(insn_in)) & "0000", 64)));
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when CONST_DXHI4 =>
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ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0004", 64)));
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when CONST_M1 =>
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ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
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when CONST_SH =>
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ret := ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
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when CONST_SH32 =>
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ret := ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
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when SPR =>
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-- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
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-- If it's all 0, we don't treat it as a dependency as slow SPRs
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-- operations are single issue.
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assert is_fast_spr(ispr) = '1' or ispr = "0000000"
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report "Decode B says SPR but ISPR is invalid:" &
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to_hstring(ispr) severity failure;
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ret := (is_fast_spr(ispr), ispr, reg_data);
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when NONE =>
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ret := ('0', (others => '0'), (others => '0'));
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end case;
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return ret;
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end;
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function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RS =>
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return ('1', gpr_to_gspr(insn_rs(insn_in)), reg_data);
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when RCR =>
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return ('1', gpr_to_gspr(insn_rcreg(insn_in)), reg_data);
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when FRS =>
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if HAS_FPU then
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return ('1', fpr_to_gspr(insn_frt(insn_in)), reg_data);
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else
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return ('0', (others => '0'), (others => '0'));
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end if;
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when FRC =>
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if HAS_FPU then
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return ('1', fpr_to_gspr(insn_frc(insn_in)), reg_data);
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else
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return ('0', (others => '0'), (others => '0'));
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end if;
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
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ispr : gspr_index_t) return decode_output_reg_t is
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begin
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case t is
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when RT =>
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return ('1', gpr_to_gspr(insn_rt(insn_in)));
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when RA =>
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return ('1', gpr_to_gspr(insn_ra(insn_in)));
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when FRT =>
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if HAS_FPU then
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return ('1', fpr_to_gspr(insn_frt(insn_in)));
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else
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return ('0', "0000000");
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end if;
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when SPR =>
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-- ISPR must be either a valid fast SPR number or all 0 for a slow SPR.
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-- If it's all 0, we don't treat it as a dependency as slow SPRs
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-- operations are single issue.
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assert is_fast_spr(ispr) = '1' or ispr = "0000000"
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report "Decode B says SPR but ISPR is invalid:" &
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to_hstring(ispr) severity failure;
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return (is_fast_spr(ispr), ispr);
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when NONE =>
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return ('0', "0000000");
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end case;
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end;
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function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
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begin
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case t is
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when RC =>
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return insn_rc(insn_in);
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when ONE =>
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return '1';
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when NONE =>
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return '0';
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end case;
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end;
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-- control signals that are derived from insn_type
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type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);
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constant result_select : mux_select_array_t := (
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OP_AND => "001", -- logical_result
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OP_OR => "001",
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OP_XOR => "001",
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OP_POPCNT => "001",
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OP_PRTY => "001",
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OP_CMPB => "001",
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OP_EXTS => "001",
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OP_BPERM => "001",
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OP_BCD => "001",
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OP_MTSPR => "001",
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OP_RLC => "010", -- rotator_result
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OP_RLCL => "010",
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OP_RLCR => "010",
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OP_SHL => "010",
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OP_SHR => "010",
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OP_EXTSWSLI => "010",
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OP_MUL_L64 => "011", -- muldiv_result
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OP_MUL_H64 => "011",
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OP_MUL_H32 => "011",
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OP_DIV => "011",
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OP_DIVE => "011",
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OP_MOD => "011",
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OP_CNTZ => "100", -- countzero_result
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OP_MFSPR => "101", -- spr_result
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OP_B => "110", -- next_nia
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OP_BC => "110",
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OP_BCREG => "110",
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OP_ADDG6S => "111", -- misc_result
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OP_ISEL => "111",
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OP_DARN => "111",
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OP_MFMSR => "111",
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OP_MFCR => "111",
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OP_SETB => "111",
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others => "000" -- default to adder_result
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);
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constant subresult_select : mux_select_array_t := (
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OP_MUL_L64 => "000", -- muldiv_result
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OP_MUL_H64 => "001",
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OP_MUL_H32 => "010",
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OP_DIV => "011",
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OP_DIVE => "011",
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OP_MOD => "011",
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OP_ADDG6S => "001", -- misc_result
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OP_ISEL => "010",
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OP_DARN => "011",
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OP_MFMSR => "100",
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OP_MFCR => "101",
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OP_SETB => "110",
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OP_CMP => "000", -- cr_result
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OP_CMPRB => "001",
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OP_CMPEQB => "010",
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OP_CROP => "011",
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OP_MCRXRX => "100",
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OP_MTCRF => "101",
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others => "000"
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);
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-- issue control signals
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signal control_valid_in : std_ulogic;
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signal control_valid_out : std_ulogic;
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signal control_stall_out : std_ulogic;
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signal control_sgl_pipe : std_logic;
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signal gpr_write_valid : std_ulogic;
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signal gpr_write : gspr_index_t;
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signal gpr_a_read_valid : std_ulogic;
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signal gpr_a_read : gspr_index_t;
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signal gpr_a_bypass : std_ulogic;
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signal gpr_b_read_valid : std_ulogic;
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signal gpr_b_read : gspr_index_t;
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signal gpr_b_bypass : std_ulogic;
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signal gpr_c_read_valid : std_ulogic;
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signal gpr_c_read : gspr_index_t;
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signal gpr_c_bypass : std_ulogic;
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signal cr_read_valid : std_ulogic;
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signal cr_write_valid : std_ulogic;
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signal cr_bypass : std_ulogic;
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signal instr_tag : instr_tag_t;
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begin
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control_0: entity work.control
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generic map (
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EX1_BYPASS => EX1_BYPASS
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)
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port map (
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clk => clk,
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rst => rst,
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complete_in => complete_in,
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valid_in => control_valid_in,
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repeated => r.repeat,
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busy_in => busy_in,
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deferred => deferred,
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flush_in => flush_in,
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sgl_pipe_in => control_sgl_pipe,
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stop_mark_in => d_in.stop_mark,
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write,
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gpr_a_read_valid_in => gpr_a_read_valid,
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gpr_a_read_in => gpr_a_read,
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gpr_b_read_valid_in => gpr_b_read_valid,
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gpr_b_read_in => gpr_b_read,
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gpr_c_read_valid_in => gpr_c_read_valid,
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gpr_c_read_in => gpr_c_read,
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execute_next_tag => execute_bypass.tag,
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execute_next_cr_tag => execute_cr_bypass.tag,
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cr_read_in => cr_read_valid,
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cr_write_in => cr_write_valid,
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cr_bypass => cr_bypass,
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valid_out => control_valid_out,
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stall_out => control_stall_out,
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stopped_out => stopped_out,
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gpr_bypass_a => gpr_a_bypass,
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gpr_bypass_b => gpr_b_bypass,
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gpr_bypass_c => gpr_c_bypass,
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instr_tag_out => instr_tag
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);
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deferred <= r.e.valid and busy_in;
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decode2_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or flush_in = '1' or deferred = '0' then
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if rin.e.valid = '1' then
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report "execute " & to_hstring(rin.e.nia);
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end if;
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r <= rin;
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end if;
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end if;
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end process;
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c_out.read <= d_in.decode.input_cr;
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decode2_1: process(all)
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variable v : reg_type;
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variable mul_a : std_ulogic_vector(63 downto 0);
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variable mul_b : std_ulogic_vector(63 downto 0);
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variable decoded_reg_a : decode_input_reg_t;
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variable decoded_reg_b : decode_input_reg_t;
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variable decoded_reg_c : decode_input_reg_t;
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variable decoded_reg_o : decode_output_reg_t;
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variable length : std_ulogic_vector(3 downto 0);
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variable op : insn_type_t;
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begin
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v := r;
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v.e := Decode2ToExecute1Init;
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mul_a := (others => '0');
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mul_b := (others => '0');
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--v.e.input_cr := d_in.decode.input_cr;
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v.e.output_cr := d_in.decode.output_cr;
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-- Work out whether XER common bits are set
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v.e.output_xer := d_in.decode.output_carry;
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case d_in.decode.insn_type is
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when OP_ADD | OP_MUL_L64 | OP_DIV | OP_DIVE =>
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-- OE field is valid in OP_ADD/OP_MUL_L64 with major opcode 31 only
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if d_in.insn(31 downto 26) = "011111" and insn_oe(d_in.insn) = '1' then
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v.e.oe := '1';
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v.e.output_xer := '1';
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end if;
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when OP_MTSPR =>
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if decode_spr_num(d_in.insn) = SPR_XER then
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v.e.output_xer := '1';
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end if;
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when others =>
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end case;
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decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data, d_in.ispr1,
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d_in.nia);
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decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data, d_in.ispr2);
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decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
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decoded_reg_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn, d_in.ispro);
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if d_in.decode.lr = '1' then
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v.e.lr := insn_lk(d_in.insn);
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-- b and bc have even major opcodes; bcreg is considered absolute
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v.e.br_abs := insn_aa(d_in.insn) or d_in.insn(26);
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end if;
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op := d_in.decode.insn_type;
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if d_in.decode.repeat /= NONE then
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v.e.repeat := '1';
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v.e.second := r.repeat;
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case d_in.decode.repeat is
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when DRSE =>
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-- do RS|1,RS for LE; RS,RS|1 for BE
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if r.repeat = d_in.big_endian then
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decoded_reg_c.reg(0) := '1';
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end if;
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when DRTE =>
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-- do RT|1,RT for LE; RT,RT|1 for BE
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if r.repeat = d_in.big_endian then
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decoded_reg_o.reg(0) := '1';
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end if;
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when DUPD =>
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-- update-form loads, 2nd instruction writes RA
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if r.repeat = '1' then
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decoded_reg_o.reg := decoded_reg_a.reg;
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end if;
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when others =>
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end case;
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elsif v.e.lr = '1' and decoded_reg_a.reg_valid = '1' then
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-- bcl/bclrl/bctarl that needs to write both CTR and LR has to be doubled
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v.e.repeat := '1';
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v.e.second := r.repeat;
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-- first one does CTR, second does LR
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decoded_reg_o.reg(0) := not r.repeat;
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end if;
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r_out.read1_enable <= decoded_reg_a.reg_valid and d_in.valid;
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r_out.read1_reg <= decoded_reg_a.reg;
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r_out.read2_enable <= decoded_reg_b.reg_valid and d_in.valid;
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r_out.read2_reg <= decoded_reg_b.reg;
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r_out.read3_enable <= decoded_reg_c.reg_valid and d_in.valid;
|
|
r_out.read3_reg <= decoded_reg_c.reg;
|
|
|
|
case d_in.decode.length is
|
|
when is1B =>
|
|
length := "0001";
|
|
when is2B =>
|
|
length := "0010";
|
|
when is4B =>
|
|
length := "0100";
|
|
when is8B =>
|
|
length := "1000";
|
|
when NONE =>
|
|
length := "0000";
|
|
end case;
|
|
|
|
-- execute unit
|
|
v.e.nia := d_in.nia;
|
|
v.e.unit := d_in.decode.unit;
|
|
v.e.fac := d_in.decode.facility;
|
|
v.e.instr_tag := instr_tag;
|
|
v.e.read_reg1 := decoded_reg_a.reg;
|
|
v.e.read_reg2 := decoded_reg_b.reg;
|
|
v.e.write_reg := decoded_reg_o.reg;
|
|
v.e.write_reg_enable := decoded_reg_o.reg_valid;
|
|
v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
|
|
v.e.xerc := c_in.read_xerc_data;
|
|
v.e.invert_a := d_in.decode.invert_a;
|
|
v.e.addm1 := '0';
|
|
v.e.insn_type := op;
|
|
v.e.invert_out := d_in.decode.invert_out;
|
|
v.e.input_carry := d_in.decode.input_carry;
|
|
v.e.output_carry := d_in.decode.output_carry;
|
|
v.e.is_32bit := d_in.decode.is_32bit;
|
|
v.e.is_signed := d_in.decode.is_signed;
|
|
v.e.insn := d_in.insn;
|
|
v.e.data_len := length;
|
|
v.e.byte_reverse := d_in.decode.byte_reverse;
|
|
v.e.sign_extend := d_in.decode.sign_extend;
|
|
v.e.update := d_in.decode.update;
|
|
v.e.reserve := d_in.decode.reserve;
|
|
v.e.br_pred := d_in.br_pred;
|
|
v.e.result_sel := result_select(op);
|
|
v.e.sub_select := subresult_select(op);
|
|
if op = OP_BC or op = OP_BCREG then
|
|
if d_in.insn(23) = '0' and r.repeat = '0' and
|
|
not (d_in.decode.insn_type = OP_BCREG and d_in.insn(10) = '0') then
|
|
-- decrement CTR if BO(2) = 0 and not bcctr
|
|
v.e.addm1 := '1';
|
|
v.e.result_sel := "000"; -- select adder output
|
|
end if;
|
|
end if;
|
|
|
|
-- See if any of the operands can get their value via the bypass path.
|
|
case gpr_a_bypass is
|
|
when '1' =>
|
|
v.e.read_data1 := execute_bypass.data;
|
|
when others =>
|
|
v.e.read_data1 := decoded_reg_a.data;
|
|
end case;
|
|
case gpr_b_bypass is
|
|
when '1' =>
|
|
v.e.read_data2 := execute_bypass.data;
|
|
when others =>
|
|
v.e.read_data2 := decoded_reg_b.data;
|
|
end case;
|
|
case gpr_c_bypass is
|
|
when '1' =>
|
|
v.e.read_data3 := execute_bypass.data;
|
|
when others =>
|
|
v.e.read_data3 := decoded_reg_c.data;
|
|
end case;
|
|
|
|
v.e.cr := c_in.read_cr_data;
|
|
if cr_bypass = '1' then
|
|
v.e.cr := execute_cr_bypass.data;
|
|
end if;
|
|
|
|
-- issue control
|
|
control_valid_in <= d_in.valid;
|
|
control_sgl_pipe <= d_in.decode.sgl_pipe;
|
|
|
|
gpr_write_valid <= v.e.write_reg_enable;
|
|
gpr_write <= decoded_reg_o.reg;
|
|
|
|
gpr_a_read_valid <= decoded_reg_a.reg_valid;
|
|
gpr_a_read <= decoded_reg_a.reg;
|
|
|
|
gpr_b_read_valid <= decoded_reg_b.reg_valid;
|
|
gpr_b_read <= decoded_reg_b.reg;
|
|
|
|
gpr_c_read_valid <= decoded_reg_c.reg_valid;
|
|
gpr_c_read <= decoded_reg_c.reg;
|
|
|
|
cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
|
|
-- Since ops that write CR only write some of the fields,
|
|
-- any op that writes CR effectively also reads it.
|
|
cr_read_valid <= cr_write_valid or d_in.decode.input_cr;
|
|
|
|
v.e.valid := control_valid_out;
|
|
if control_valid_out = '1' then
|
|
v.repeat := v.e.repeat and not r.repeat;
|
|
end if;
|
|
|
|
stall_out <= control_stall_out or v.repeat;
|
|
|
|
if rst = '1' or flush_in = '1' then
|
|
v.e := Decode2ToExecute1Init;
|
|
v.repeat := '0';
|
|
end if;
|
|
|
|
-- Update registers
|
|
rin <= v;
|
|
|
|
-- Update outputs
|
|
e_out <= r.e;
|
|
end process;
|
|
|
|
d2_log: if LOG_LENGTH > 0 generate
|
|
signal log_data : std_ulogic_vector(9 downto 0);
|
|
begin
|
|
dec2_log : process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
log_data <= r.e.nia(5 downto 2) &
|
|
r.e.valid &
|
|
stopped_out &
|
|
stall_out &
|
|
gpr_a_bypass &
|
|
gpr_b_bypass &
|
|
gpr_c_bypass;
|
|
end if;
|
|
end process;
|
|
log_out <= log_data;
|
|
end generate;
|
|
|
|
end architecture behaviour;
|