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45 lines
1.0 KiB
VHDL
45 lines
1.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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entity logical is
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port (
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rs : in std_ulogic_vector(63 downto 0);
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rb : in std_ulogic_vector(63 downto 0);
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op : in insn_type_t;
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invert_in : in std_ulogic;
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invert_out : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity logical;
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architecture behaviour of logical is
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begin
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logical_0: process(all)
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variable rb_adj, tmp : std_ulogic_vector(63 downto 0);
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begin
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rb_adj := rb;
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if invert_in = '1' then
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rb_adj := not rb;
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end if;
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case op is
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when OP_AND =>
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tmp := rs and rb_adj;
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when OP_OR =>
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tmp := rs or rb_adj;
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when others =>
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tmp := rs xor rb_adj;
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end case;
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result <= tmp;
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if invert_out = '1' then
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result <= not tmp;
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end if;
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end process;
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end behaviour;
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