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Paul Mackerras ca4eb46aea Make wishbone addresses be in units of doublewords or words ... This makes the 64-bit wishbone buses have the address expressed in units of doublewords (64 bits), and similarly for the 32-bit buses the address is in units of words (32 bits). This is to comply with the wishbone spec. Previously the addresses on the wishbone buses were in units of bytes regardless of the bus data width, which is not correct and caused problems with interfacing with externally-generated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		3 years ago
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sdram_init	litedram: Add sdcard to soc features	3 years ago
acorn-cle-215.yml	litedram: Update yaml files	3 years ago
arty.yml	litedram: Update yaml files	3 years ago
dram-init-mem.vhdl	Make wishbone addresses be in units of doublewords or words	3 years ago
generate.py	litedram: Fix compiler warning	3 years ago
genesys2.yml	litedram: Update yaml files	3 years ago
nexys-video.yml	litedram: Update yaml files	3 years ago
no-init-mem.vhdl	litedram: Split the init memory from the main wrapper	5 years ago
sim.yml	litedram: Update yaml files	3 years ago