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242 lines
7.1 KiB
VHDL
242 lines
7.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity simple_ram_behavioural_tb is
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end simple_ram_behavioural_tb;
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architecture behave of simple_ram_behavioural_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic := '1';
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constant clk_period : time := 10 ns;
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signal w_in : wishbone_slave_out;
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signal w_out : wishbone_master_out;
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begin
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simple_ram_0: entity work.mw_soc_memory
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generic map (
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RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",
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MEMORY_SIZE => 16
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)
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port map (
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clk => clk,
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rst => rst,
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wishbone_out => w_in,
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wishbone_in => w_out
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);
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clock: process
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begin
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clk <= '1';
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wait for clk_period / 2;
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clk <= '0';
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wait for clk_period / 2;
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end process clock;
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stim: process
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begin
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w_out.adr <= (others => '0');
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w_out.dat <= (others => '0');
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w_out.cyc <= '0';
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w_out.stb <= '0';
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w_out.sel <= (others => '0');
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w_out.we <= '0';
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wait for clk_period;
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rst <= '0';
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wait for clk_period;
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w_out.cyc <= '1';
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-- test various read lengths and alignments
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000011";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00001111";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= x"0000000000000000";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= x"0000000000000001";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= x"0000000000000007";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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-- test various write lengths and alignments
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000000";
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w_out.we <= '1';
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w_out.dat(7 downto 0) <= x"0F";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "00000001";
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w_out.adr <= x"0000000000000000";
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w_out.we <= '0';
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= x"0000000000000007";
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w_out.we <= '1';
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w_out.dat <= x"BADC0FFEBADC0FFE";
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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w_out.stb <= '1';
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w_out.sel <= "11111111";
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w_out.adr <= x"0000000000000007";
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w_out.we <= '0';
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assert w_in.ack = '0';
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wait for clk_period;
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assert w_in.ack = '1';
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assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
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w_out.stb <= '0';
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wait for clk_period;
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assert w_in.ack = '0';
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assert false report "end of test" severity failure;
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wait;
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end process;
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end behave;
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