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270 lines
8.1 KiB
VHDL
270 lines
8.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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use work.insn_helpers.all;
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entity rotator_tb is
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end rotator_tb;
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architecture behave of rotator_tb is
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constant clk_period: time := 10 ns;
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signal ra, rs: std_ulogic_vector(63 downto 0);
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signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
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signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
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signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
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signal result: std_ulogic_vector(63 downto 0);
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signal carry_out: std_ulogic;
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begin
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rotator_0: entity work.rotator
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port map (
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rs => rs,
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ra => ra,
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shift => shift,
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insn => insn,
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is_32bit => is_32bit,
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right_shift => right_shift,
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arith => arith,
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clear_left => clear_left,
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clear_right => clear_right,
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result => result,
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carry_out => carry_out
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);
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stim_process: process
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variable behave_ra: std_ulogic_vector(63 downto 0);
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variable behave_ca_ra: std_ulogic_vector(64 downto 0);
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begin
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-- rlwinm, rlwnm
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report "test rlw[i]nm";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rlwnm_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rlwimi
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report "test rlwimi";
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rlwimi_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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ra <= pseudorand(64);
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shift <= "00" & pseudorand(5);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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assert behave_ra = result
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report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldicl, rldcl
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report "test rld[i]cl";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '0';
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rldicl_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldicr, rldcr
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report "test rld[i]cr";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '1';
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rldicr_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "insn me = " & to_hstring(insn_me(insn));
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--report "result = " & to_hstring(result);
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assert behave_ra = result
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report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldic
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report "test rldic";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldic_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- rldimi
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report "test rldimi";
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldimi_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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ra <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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insn <= x"00000" & '0' & pseudorand(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
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assert behave_ra = result
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report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- slw
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report "test slw";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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slw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- sld
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report "test sld";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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sld_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- srw
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report "test srw";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- srd
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report "test srd";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srd_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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assert behave_ra = result
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report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
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end loop;
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-- sraw[i]
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report "test sraw[i]";
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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sraw_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= '0' & pseudorand(6);
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wait for clk_period;
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behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
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report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
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end loop;
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-- srad[i]
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report "test srad[i]";
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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srad_loop : for i in 0 to 1000 loop
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rs <= pseudorand(64);
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shift <= pseudorand(7);
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wait for clk_period;
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behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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--report "rs = " & to_hstring(rs);
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--report "ra = " & to_hstring(ra);
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--report "shift = " & to_hstring(shift);
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--report "result = " & to_hstring(carry_out & result);
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assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
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report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
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end loop;
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assert false report "end of test" severity failure;
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wait;
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end process;
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end behave;
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