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			183 lines
		
	
	
		
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			Plaintext
		
	
			
		
		
	
	
			183 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			Plaintext
		
	
| CAPI=2:
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| 
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| name : ::microwatt:0
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| 
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| filesets:
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|   core:
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|     files:
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|       - decode_types.vhdl
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|       - wishbone_types.vhdl
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|       - common.vhdl
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|       - fetch1.vhdl
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|       - fetch2.vhdl
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|       - decode1.vhdl
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|       - helpers.vhdl
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|       - decode2.vhdl
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|       - register_file.vhdl
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|       - cr_file.vhdl
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|       - crhelpers.vhdl
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|       - ppc_fx_insns.vhdl
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|       - sim_console.vhdl
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|       - logical.vhdl
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|       - countzero.vhdl
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|       - gpr_hazard.vhdl
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|       - cr_hazard.vhdl
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|       - control.vhdl
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|       - execute1.vhdl
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|       - execute2.vhdl
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|       - loadstore1.vhdl
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|       - loadstore2.vhdl
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|       - multiply.vhdl
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|       - divider.vhdl
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|       - rotator.vhdl
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|       - writeback.vhdl
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|       - insn_helpers.vhdl
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|       - core.vhdl
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|       - icache.vhdl
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|       - plru.vhdl
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|       - cache_ram.vhdl
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|       - core_debug.vhdl
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|     file_type : vhdlSource-2008
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| 
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|   soc:
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|     files:
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|       - wishbone_arbiter.vhdl
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|       - wishbone_debug_master.vhdl
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|       - soc.vhdl
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|     file_type : vhdlSource-2008
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| 
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|   fpga:
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|     files:
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|       - fpga/pp_fifo.vhd
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|       - fpga/mw_soc_memory.vhdl
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|       - fpga/soc_reset.vhdl
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|       - fpga/pp_soc_uart.vhd
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|       - fpga/pp_utilities.vhd
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|       - fpga/toplevel.vhdl
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|       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
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|     file_type : vhdlSource-2008
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| 
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|   debug_xilinx:
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|     files:
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|       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
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| 
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|   debug_dummy:
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|     files:
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|       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
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| 
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|   nexys_a7:
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|     files:
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|       - fpga/nexys_a7.xdc : {file_type : xdc}
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|       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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| 
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|   nexys_video:
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|     files:
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|       - fpga/nexys-video.xdc : {file_type : xdc}
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|       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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| 
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|   arty_a7:
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|     files:
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|       - fpga/arty_a7.xdc : {file_type : xdc}
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|       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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| 
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|   cmod_a7-35:
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|     files:
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|       - fpga/cmod_a7-35.xdc : {file_type : xdc}
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|       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
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| 
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| targets:
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|   nexys_a7:
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|     default_tool: vivado
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|     filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
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|     parameters :
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|       - memory_size
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|       - ram_init_file
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|       - clk_input
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|       - clk_frequency
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|     tools:
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|       vivado: {part : xc7a100tcsg324-1}
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|     toplevel : toplevel
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| 
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|   nexys_video:
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|     default_tool: vivado
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|     filesets: [core, nexys_video, soc, fpga, debug_xilinx]
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|     parameters :
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|       - memory_size
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|       - ram_init_file
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|       - clk_input
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|       - clk_frequency
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|     tools:
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|       vivado: {part : xc7a200tsbg484-1}
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|     toplevel : toplevel
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| 
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|   arty_a7-35:
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|     default_tool: vivado
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|     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
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|     parameters :
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|       - memory_size
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|       - ram_init_file
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|       - clk_input
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|       - clk_frequency
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|     tools:
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|       vivado: {part : xc7a35ticsg324-1L}
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|     toplevel : toplevel
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| 
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|   arty_a7-100:
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|     default_tool: vivado
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|     filesets: [core, arty_a7, soc, fpga, debug_xilinx]
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|     parameters :
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|       - memory_size
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|       - ram_init_file
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|       - clk_input
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|       - clk_frequency
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|     tools:
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|       vivado: {part : xc7a100ticsg324-1L}
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|     toplevel : toplevel
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| 
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|   cmod_a7-35:
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|     default_tool: vivado
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|     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
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|     parameters :
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|       - memory_size
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|       - ram_init_file
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|       - reset_low=false
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|       - clk_input=12000000
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|       - clk_frequency
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|     tools:
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|       vivado: {part : xc7a35tcpg236-1}
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|     toplevel : toplevel
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| 
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|   synth:
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|     filesets: [core, soc]
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|     tools:
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|       vivado: {pnr : none}
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|     toplevel: core
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| 
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| parameters:
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|   memory_size:
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|     datatype    : int
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|     description : On-chip memory size (bytes)
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|     paramtype   : generic
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| 
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|   ram_init_file:
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|     datatype    : file
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|     description : Initial on-chip RAM contents
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|     paramtype   : generic
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| 
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|   reset_low:
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|     datatype    : bool
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|     description : External reset button polarity
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|     paramtype   : generic
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| 
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|   clk_input:
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|     datatype    : int
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|     description : Clock input frequency in HZ (for top-generic based boards)
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|     paramtype   : generic
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|     default     : 100000000
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| 
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|   clk_frequency:
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|     datatype    : int
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|     description : Generated system clock frequency in HZ (for top-generic based boards)
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|     paramtype   : generic
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|     default     : 50000000
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