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58 lines
1.3 KiB
VHDL
58 lines
1.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.crhelpers.all;
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use work.ppc_fx_insns.all;
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-- 2 cycle ALU
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-- We handle rc form instructions here
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entity execute2 is
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port (
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clk : in std_ulogic;
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e_in : in Execute1ToExecute2Type;
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e_out : out Execute2ToWritebackType
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);
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end execute2;
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architecture behave of execute2 is
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signal r, rin : Execute2ToWritebackType;
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begin
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execute2_0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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execute2_1: process(all)
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variable v : Execute2ToWritebackType;
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begin
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v := rin;
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v.valid := e_in.valid;
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v.write_enable := e_in.write_enable;
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v.write_reg := e_in.write_reg;
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v.write_data := e_in.write_data;
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v.write_cr_enable := e_in.write_cr_enable;
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v.write_cr_mask := e_in.write_cr_mask;
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v.write_cr_data := e_in.write_cr_data;
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if e_in.valid = '1' and e_in.rc = '1' then
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v.write_cr_enable := '1';
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v.write_cr_mask := num_to_fxm(0);
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v.write_cr_data := ppc_cmpi('1', e_in.write_data, x"0000") & x"0000000";
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end if;
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-- Update registers
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rin <= v;
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-- Update outputs
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e_out <= r;
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end process;
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end;
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