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115 lines
3.0 KiB
VHDL
115 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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entity zero_counter is
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port (
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rs : in std_ulogic_vector(63 downto 0);
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count_right : in std_ulogic;
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is_32bit : in std_ulogic;
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result : out std_ulogic_vector(63 downto 0)
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);
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end entity zero_counter;
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architecture behaviour of zero_counter is
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signal y, z : std_ulogic_vector(3 downto 0);
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signal v16 : std_ulogic_vector(15 downto 0);
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signal v4 : std_ulogic_vector(3 downto 0);
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signal sel : std_ulogic_vector(5 downto 0);
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-- Return the index of the leftmost or rightmost 1 in a set of 4 bits.
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-- Assumes v is not "0000"; if it is, return (right ? "11" : "00").
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function encoder(v: std_ulogic_vector(3 downto 0); right: std_ulogic) return std_ulogic_vector is
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begin
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if right = '0' then
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if v(3) = '1' then
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return "11";
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elsif v(2) = '1' then
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return "10";
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elsif v(1) = '1' then
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return "01";
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else
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return "00";
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end if;
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else
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if v(0) = '1' then
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return "00";
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elsif v(1) = '1' then
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return "01";
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elsif v(2) = '1' then
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return "10";
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else
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return "11";
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end if;
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end if;
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end;
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begin
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zerocounter0: process(all)
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begin
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-- Test 4 groups of 16 bits each.
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-- The top 2 groups are considered to be zero in 32-bit mode.
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z(0) <= or (rs(15 downto 0));
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z(1) <= or (rs(31 downto 16));
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z(2) <= or (rs(47 downto 32));
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z(3) <= or (rs(63 downto 48));
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if is_32bit = '0' then
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sel(5 downto 4) <= encoder(z, count_right);
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else
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sel(5) <= '0';
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if count_right = '0' then
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sel(4) <= z(1);
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else
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sel(4) <= not z(0);
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end if;
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end if;
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-- Select the leftmost/rightmost non-zero group of 16 bits
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case sel(5 downto 4) is
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when "00" =>
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v16 <= rs(15 downto 0);
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when "01" =>
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v16 <= rs(31 downto 16);
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when "10" =>
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v16 <= rs(47 downto 32);
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when others =>
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v16 <= rs(63 downto 48);
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end case;
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-- Test 4 groups of 4 bits
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y(0) <= or (v16(3 downto 0));
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y(1) <= or (v16(7 downto 4));
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y(2) <= or (v16(11 downto 8));
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y(3) <= or (v16(15 downto 12));
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sel(3 downto 2) <= encoder(y, count_right);
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-- Select the leftmost/rightmost non-zero group of 4 bits
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case sel(3 downto 2) is
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when "00" =>
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v4 <= v16(3 downto 0);
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when "01" =>
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v4 <= v16(7 downto 4);
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when "10" =>
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v4 <= v16(11 downto 8);
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when others =>
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v4 <= v16(15 downto 12);
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end case;
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sel(1 downto 0) <= encoder(v4, count_right);
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-- sel is now the index of the leftmost/rightmost 1 bit in rs
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if v4 = "0000" then
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-- operand is zero, return 32 for 32-bit, else 64
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result <= x"00000000000000" & '0' & not is_32bit & is_32bit & "00000";
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elsif count_right = '0' then
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-- return (63 - sel), trimmed to 5 bits in 32-bit mode
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result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
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else
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result <= x"00000000000000" & "00" & sel;
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end if;
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end process;
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end behaviour;
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