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Benjamin Herrenschmidt bd42580a42 pp_fifo: Fix full fifo losing all data on simultaneous push & pop ... The pp_fifo decides whether top = bottom means empty or full based on whether the previous operation was a push or a pop. If the fifo performs both in one cycle, it sets the previous op to pop. That means that a full fifo being added a character and removed one at the same time becomes empty. Instead, just leave the previous op alone. If the fifo was empty, it remains so, if it was full ditto. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
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LICENSE	Initial import of microwatt	5 years ago
arty_a7.xdc	fpga: Hookup Arty to litedram	5 years ago
clk_gen_bypass.vhd	Fix clk_gen_bypass	5 years ago
clk_gen_mcmm.vhd	Improve PLL/MMCM clocks configuration	5 years ago
clk_gen_plle2.vhd	Improve PLL/MMCM clocks configuration	5 years ago
cmod_a7-35.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
firmware.hex	Add a few more FPGA related files	5 years ago
hello_world.hex	hello_world: Use new headers and frequency from syscon	5 years ago
main_bram.vhdl	Fix some ghdlsynth issues with fpga_bram	5 years ago
nexys-video.xdc	fpga: Hookup nexys-video to litedram	5 years ago
nexys_a7.xdc	Add SPI configuration to Xilinx constraint files	5 years ago
pp_fifo.vhd	pp_fifo: Fix full fifo losing all data on simultaneous push & pop	5 years ago
pp_soc_uart.vhd	Add a few FFs on the RX input to avoid metastability issues	5 years ago
pp_utilities.vhd	Initial import of microwatt	5 years ago
soc_reset.vhdl	Rework SOC reset	5 years ago
soc_reset_tb.vhdl	Rework SOC reset	5 years ago
top-arty.vhdl	syscon: Add syscon registers	5 years ago
top-generic.vhdl	fpga: Hookup Arty to litedram	5 years ago
top-nexys-video.vhdl	syscon: Add syscon registers	5 years ago