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A tiny Open POWER ISA softcore written in VHDL 2008
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VHDL 14.8%
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Assembly 0.6%
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Paul Mackerras bbae2d1eda decode: Index minor op table with insn bits for opcode 31 
This changes decode_op_31_array from being indexed by a ppc_insn_t
(which is derived from the instruction word by a whole series of
if/elsif statements) to being indexed directly by bits 10...1 of
the instruction word.  With this we no longer need ppc_insn.

This then means that the decode1 stage doesn't distinguish between
mfcr and mfocrf, or between mtcrf and mtocrf, since those are
distinguished by the value in bit 20 of the instruction.  To
accommodate that, execute1 changes so that the one op value (OP_MFCR)
does either the mfcr or the mfocrf behaviour depending on bit 20
of the instruction word; and similarly for mtcrf/mtocrf.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
fpga Improve PLL/MMCM clocks configuration
hello_world Rebuild hello world assuming a 50MHz clock
scripts New C based JTAG debug tool
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests Initial import of microwatt
.gitignore Add new files to git ignore
.travis.yml Allow a full make check on Travis
LICENSE Initial import of microwatt
Makefile decode: Push mtspr/mfspr register decoding down into execute1
README.md Remove gcc software divide patch
common.vhdl decode: Push mtspr/mfspr register decoding down into execute1
core.vhdl Merge branch 'divider' of https://github.com/paulusmack/microwatt
core_debug.vhdl Add core debug module
core_tb.vhdl Add core debug module
cr_file.vhdl Reformat CR file
crhelpers.vhdl Reformat crhelpers, and remove some stale code
decode1.vhdl decode: Index minor op table with insn bits for opcode 31
decode2.vhdl decode: Push mtspr/mfspr register decoding down into execute1
decode_types.vhdl decode: Index minor op table with insn bits for opcode 31
divider.vhdl divider: Do absolute-value ops in divider instead of decode
divider_tb.vhdl divider: Do absolute-value ops in divider instead of decode
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl Wishbone debug module
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously
execute1.vhdl decode: Index minor op table with insn bits for opcode 31
execute2.vhdl Reformat execute2
fetch1.vhdl Simplify fetch1
fetch2.vhdl Reformat fetch2
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
helpers.vhdl Reformat helpers
icache.vhdl Add a simple direct mapped icache
icache_tb.vhdl Add an icache testbench
insn_helpers.vhdl Add MCRF instruction
loadstore1.vhdl Reformat loadstore1
loadstore2.vhdl loadstore2: Do data formatting after a register stage
microwatt.core Improve PLL/MMCM clocks configuration
multiply.vhdl Multiply needs to be 16 stages to fix all timing issues
multiply_tb.vhdl Reformat multiply_tb
ppc_fx_insns.vhdl Implement absolute branches
register_file.vhdl Reformat register file
sim_console.vhdl Reformat sim_console
sim_console_c.c Make sim poll non-blocking
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Add jtag support in simulation via a socket
sim_uart.vhdl Share soc.vhdl between FPGA and sim
simple_ram_behavioural.vhdl Reformat simple_ram_behavioural
simple_ram_behavioural_helpers.vhdl Reformat simple_ram_behavioural
simple_ram_behavioural_helpers_c.c Silence some loadstore related debug
simple_ram_behavioural_tb.bin Initial import of microwatt
simple_ram_behavioural_tb.vhdl Reformat simple_ram_behavioural
soc.vhdl Add core debug module
wishbone_arbiter.vhdl Use a 3 way WB arbiter and cleanup fpga toplevel
wishbone_debug_master.vhdl Wishbone debug module
wishbone_types.vhdl Reformat wishbone code
writeback.vhdl Add a divider unit and a testbench for it

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)