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Paul Mackerras b8f9c833f8 litedram: Split L2 PLRU into storage and logic ... As has been done for the L1 dcache and icache, this puts the L2 cache PLRU state into a little RAM and has a single copy of the logic to calculate the pseudo-LRU way and update the PLRU state. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		2 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	4 years ago
litedram-wrapper-l2.vhdl	litedram: Split L2 PLRU into storage and logic	2 years ago
sim_dram_verilate.mk	litedram: Add simulation support	4 years ago
sim_litedram.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	2 years ago
sim_litedram_c.cpp	Fix build of core_dram_tb and dram_tb and fix tracing	2 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	4 years ago
wave.opt	litedram: Add an L2 cache with store queue	4 years ago
wave_tb.gtkw	litedram: l2: Latency improvements	4 years ago