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278 lines
9.3 KiB
VHDL
278 lines
9.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.helpers.all;
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-- 2 cycle LSU
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-- We calculate the address in the first cycle
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entity loadstore1 is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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l_in : in Execute1ToLoadstore1Type;
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l_out : out Loadstore1ToWritebackType;
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d_out : out Loadstore1ToDcacheType;
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d_in : in DcacheToLoadstore1Type;
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dc_stall : in std_ulogic;
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stall_out : out std_ulogic
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);
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end loadstore1;
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-- Note, we don't currently use the stall output from the dcache because
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-- we know it can take two requests without stalling when idle, we are
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-- its only user, and we know it never stalls when idle.
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architecture behave of loadstore1 is
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-- State machine for unaligned loads/stores
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type state_t is (IDLE, -- ready for instruction
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SECOND_REQ, -- send 2nd request of unaligned xfer
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FIRST_ACK_WAIT, -- waiting for 1st ack from dcache
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LAST_ACK_WAIT, -- waiting for last ack from dcache
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LD_UPDATE -- writing rA with computed addr on load
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);
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type reg_stage_t is record
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-- latch most of the input request
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load : std_ulogic;
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addr : std_ulogic_vector(63 downto 0);
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data : std_ulogic_vector(63 downto 0);
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write_reg : gpr_index_t;
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length : std_ulogic_vector(3 downto 0);
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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update_reg : gpr_index_t;
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xerc : xer_common_t;
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reserve : std_ulogic;
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rc : std_ulogic;
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nc : std_ulogic; -- non-cacheable access
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state : state_t;
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second_bytes : std_ulogic_vector(7 downto 0);
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end record;
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signal r, rin : reg_stage_t;
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signal lsu_sum : std_ulogic_vector(63 downto 0);
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-- Generate byte enables from sizes
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function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
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begin
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case length is
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when "0001" =>
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return "00000001";
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when "0010" =>
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return "00000011";
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when "0100" =>
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return "00001111";
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when "1000" =>
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return "11111111";
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when others =>
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return "00000000";
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end case;
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end function length_to_sel;
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-- Calculate byte enables
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-- This returns 16 bits, giving the select signals for two transfers,
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-- to account for unaligned loads or stores
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function xfer_data_sel(size : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(2 downto 0))
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return std_ulogic_vector is
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variable longsel : std_ulogic_vector(15 downto 0);
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begin
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longsel := "00000000" & length_to_sel(size);
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return std_ulogic_vector(shift_left(unsigned(longsel),
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to_integer(unsigned(address))));
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end function xfer_data_sel;
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begin
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-- Calculate the address in the first cycle
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lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0');
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loadstore1_0: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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r.state <= IDLE;
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else
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r <= rin;
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end if;
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end if;
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end process;
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loadstore1_1: process(all)
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variable v : reg_stage_t;
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variable brev_lenm1 : unsigned(2 downto 0);
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variable byte_offset : unsigned(2 downto 0);
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variable j : integer;
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variable k : unsigned(2 downto 0);
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variable long_sel : std_ulogic_vector(15 downto 0);
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variable byte_sel : std_ulogic_vector(7 downto 0);
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variable req : std_ulogic;
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variable stall : std_ulogic;
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variable addr : std_ulogic_vector(63 downto 0);
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variable wdata : std_ulogic_vector(63 downto 0);
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variable write_enable : std_ulogic;
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variable do_update : std_ulogic;
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variable second_dword : std_ulogic;
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variable done : std_ulogic;
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begin
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v := r;
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req := '0';
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stall := '0';
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done := '0';
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byte_sel := (others => '0');
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addr := lsu_sum;
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write_enable := '0';
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do_update := '0';
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second_dword := '0';
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case r.state is
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when IDLE =>
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if l_in.valid = '1' then
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v.load := l_in.load;
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v.addr := lsu_sum;
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v.data := l_in.data;
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v.write_reg := l_in.write_reg;
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v.length := l_in.length;
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v.byte_reverse := l_in.byte_reverse;
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v.sign_extend := l_in.sign_extend;
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v.update := l_in.update;
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v.update_reg := l_in.update_reg;
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v.xerc := l_in.xerc;
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v.reserve := l_in.reserve;
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v.rc := l_in.rc;
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-- XXX Temporary hack. Mark the op as non-cachable if the address
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-- is the form 0xc-------
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--
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-- This will have to be replaced by a combination of implementing the
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-- proper HV CI load/store instructions and having an MMU to get the I
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-- bit otherwise.
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if lsu_sum(31 downto 28) = "1100" then
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v.nc := '1';
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else
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v.nc := '0';
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end if;
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-- Do length_to_sel and work out if we are doing 2 dwords
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long_sel := xfer_data_sel(l_in.length, v.addr(2 downto 0));
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byte_sel := long_sel(7 downto 0);
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v.second_bytes := long_sel(15 downto 8);
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v.addr := lsu_sum;
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-- Do byte reversing and rotating for stores in the first cycle
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if v.load = '0' then
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byte_offset := unsigned(lsu_sum(2 downto 0));
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brev_lenm1 := "000";
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if l_in.byte_reverse = '1' then
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brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
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end if;
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for i in 0 to 7 loop
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k := (to_unsigned(i, 3) xor brev_lenm1) + byte_offset;
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j := to_integer(k) * 8;
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v.data(j + 7 downto j) := l_in.data(i * 8 + 7 downto i * 8);
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end loop;
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end if;
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req := '1';
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stall := '1';
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if long_sel(15 downto 8) = "00000000" then
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v.state := LAST_ACK_WAIT;
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else
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v.state := SECOND_REQ;
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end if;
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end if;
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when SECOND_REQ =>
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-- compute (addr + 8) & ~7 for the second doubleword when unaligned
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addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
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byte_sel := r.second_bytes;
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req := '1';
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stall := '1';
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v.state := FIRST_ACK_WAIT;
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when FIRST_ACK_WAIT =>
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stall := '1';
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if d_in.valid = '1' then
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write_enable := r.load;
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v.state := LAST_ACK_WAIT;
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end if;
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when LAST_ACK_WAIT =>
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stall := '1';
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second_dword := or (r.second_bytes);
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if d_in.valid = '1' then
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write_enable := r.load;
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if r.load = '1' and r.update = '1' then
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-- loads with rA update need an extra cycle
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v.state := LD_UPDATE;
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else
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-- stores write back rA update in this cycle
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do_update := r.update;
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stall := '0';
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done := '1';
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v.state := IDLE;
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end if;
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end if;
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when LD_UPDATE =>
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do_update := '1';
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v.state := IDLE;
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done := '1';
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end case;
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-- Update registers
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rin <= v;
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-- Update outputs to dcache
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d_out.valid <= req;
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d_out.load <= v.load;
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d_out.nc <= v.nc;
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d_out.reserve <= v.reserve;
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d_out.addr <= addr;
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d_out.data <= v.data;
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d_out.byte_sel <= byte_sel;
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-- Update outputs to writeback
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-- Multiplex either cache data to the destination GPR or
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-- the address for the rA update.
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l_out.valid <= done;
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if do_update = '1' then
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l_out.write_enable <= '1';
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l_out.write_reg <= r.update_reg;
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l_out.write_data <= r.addr;
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l_out.write_len <= x"8";
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l_out.write_shift <= "000";
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l_out.sign_extend <= '0';
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l_out.byte_reverse <= '0';
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l_out.second_word <= '0';
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l_out.rc <= '0';
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l_out.store_done <= '0';
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else
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l_out.write_enable <= write_enable;
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l_out.write_reg <= r.write_reg;
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l_out.write_data <= d_in.data;
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l_out.write_len <= r.length;
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l_out.write_shift <= r.addr(2 downto 0);
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l_out.sign_extend <= r.sign_extend;
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l_out.byte_reverse <= r.byte_reverse;
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l_out.second_word <= second_dword;
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l_out.rc <= r.rc and done;
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l_out.store_done <= d_in.store_done;
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end if;
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l_out.xerc <= r.xerc;
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stall_out <= stall;
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end process;
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end;
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