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438 lines
14 KiB
VHDL
438 lines
14 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.helpers.all;
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use work.insn_helpers.all;
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entity decode2 is
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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complete_in : in std_ulogic;
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stall_out : out std_ulogic;
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stopped_out : out std_ulogic;
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flush_in: in std_ulogic;
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d_in : in Decode1ToDecode2Type;
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e_out : out Decode2ToExecute1Type;
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m_out : out Decode2ToMultiplyType;
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d_out : out Decode2ToDividerType;
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l_out : out Decode2ToLoadstore1Type;
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r_in : in RegisterFileToDecode2Type;
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r_out : out Decode2ToRegisterFileType;
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c_in : in CrFileToDecode2Type;
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c_out : out Decode2ToCrFileType
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);
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end entity decode2;
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architecture behaviour of decode2 is
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type reg_type is record
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e : Decode2ToExecute1Type;
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m : Decode2ToMultiplyType;
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d : Decode2ToDividerType;
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l : Decode2ToLoadstore1Type;
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end record;
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signal r, rin : reg_type;
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type decode_input_reg_t is record
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reg_valid : std_ulogic;
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reg : std_ulogic_vector(4 downto 0);
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data : std_ulogic_vector(63 downto 0);
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end record;
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function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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variable is_reg : std_ulogic;
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begin
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is_reg := '0' when insn_ra(insn_in) = "00000" else '1';
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if t = RA or (t = RA_OR_ZERO and insn_ra(insn_in) /= "00000") then
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--return (is_reg, insn_ra(insn_in), reg_data);
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return ('1', insn_ra(insn_in), reg_data);
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else
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return ('0', (others => '0'), (others => '0'));
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end if;
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end;
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function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RB =>
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return ('1', insn_rb(insn_in), reg_data);
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when CONST_UI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_ui(insn_in)), 64)));
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when CONST_SI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)), 64)));
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when CONST_SI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000", 64)));
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when CONST_UI_HI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000", 64)));
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when CONST_LI =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00", 64)));
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when CONST_BD =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
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when CONST_DS =>
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return ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
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when CONST_M1 =>
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return ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
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when CONST_SH =>
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return ('0', (others => '0'), x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
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when CONST_SH32 =>
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return ('0', (others => '0'), x"00000000000000" & "000" & insn_in(15 downto 11));
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0);
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reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
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begin
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case t is
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when RS =>
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return ('1', insn_rs(insn_in), reg_data);
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when NONE =>
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return ('0', (others => '0'), (others => '0'));
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end case;
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end;
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function decode_output_reg (t : output_reg_a_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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begin
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case t is
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when RT =>
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return insn_rt(insn_in);
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when RA =>
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return insn_ra(insn_in);
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when NONE =>
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return "00000";
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end case;
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end;
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function decode_rc (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
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begin
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case t is
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when RC =>
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return insn_rc(insn_in);
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when ONE =>
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return '1';
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when NONE =>
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return '0';
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end case;
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end;
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-- For now, use "rc" in the decode table to decide whether oe exists.
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-- This is not entirely correct architecturally: For mulhd and
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-- mulhdu, the OE field is reserved. It remains to be seen what an
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-- actual POWER9 does if we set it on those instructions, for now we
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-- test that further down when assigning to the multiplier oe input.
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--
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function decode_oe (t : rc_t; insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
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begin
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case t is
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when RC =>
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return insn_oe(insn_in);
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when OTHERS =>
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return '0';
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end case;
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end;
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-- issue control signals
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signal control_valid_in : std_ulogic;
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signal control_valid_out : std_ulogic;
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signal control_sgl_pipe : std_logic;
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signal gpr_write_valid : std_ulogic;
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signal gpr_write : std_ulogic_vector(4 downto 0);
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signal gpr_a_read_valid : std_ulogic;
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signal gpr_a_read : std_ulogic_vector(4 downto 0);
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signal gpr_b_read_valid : std_ulogic;
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signal gpr_b_read : std_ulogic_vector(4 downto 0);
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signal gpr_c_read_valid : std_ulogic;
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signal gpr_c_read : std_ulogic_vector(4 downto 0);
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signal cr_write_valid : std_ulogic;
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begin
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control_0: entity work.control
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generic map (
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PIPELINE_DEPTH => 1
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)
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port map (
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clk => clk,
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rst => rst,
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complete_in => complete_in,
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valid_in => control_valid_in,
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flush_in => flush_in,
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sgl_pipe_in => control_sgl_pipe,
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stop_mark_in => d_in.stop_mark,
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gpr_write_valid_in => gpr_write_valid,
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gpr_write_in => gpr_write,
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gpr_a_read_valid_in => gpr_a_read_valid,
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gpr_a_read_in => gpr_a_read,
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gpr_b_read_valid_in => gpr_b_read_valid,
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gpr_b_read_in => gpr_b_read,
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gpr_c_read_valid_in => gpr_c_read_valid,
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gpr_c_read_in => gpr_c_read,
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cr_read_in => d_in.decode.input_cr,
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cr_write_in => cr_write_valid,
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valid_out => control_valid_out,
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stall_out => stall_out,
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stopped_out => stopped_out
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);
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decode2_0: process(clk)
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begin
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if rising_edge(clk) then
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if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' or rin.d.valid = '1' then
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report "execute " & to_hstring(rin.e.nia);
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end if;
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r <= rin;
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end if;
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end process;
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r_out.read1_reg <= insn_ra(d_in.insn);
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r_out.read2_reg <= insn_rb(d_in.insn);
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r_out.read3_reg <= insn_rs(d_in.insn);
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c_out.read <= d_in.decode.input_cr;
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decode2_1: process(all)
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variable v : reg_type;
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variable mul_a : std_ulogic_vector(63 downto 0);
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variable mul_b : std_ulogic_vector(63 downto 0);
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variable decoded_reg_a : decode_input_reg_t;
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variable decoded_reg_b : decode_input_reg_t;
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variable decoded_reg_c : decode_input_reg_t;
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variable signed_division: std_ulogic;
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variable length : std_ulogic_vector(3 downto 0);
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begin
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v := r;
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v.e := Decode2ToExecute1Init;
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v.l := Decode2ToLoadStore1Init;
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v.m := Decode2ToMultiplyInit;
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v.d := Decode2ToDividerInit;
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mul_a := (others => '0');
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mul_b := (others => '0');
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--v.e.input_cr := d_in.decode.input_cr;
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--v.m.input_cr := d_in.decode.input_cr;
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--v.e.output_cr := d_in.decode.output_cr;
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decoded_reg_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, r_in.read1_data);
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decoded_reg_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn, r_in.read2_data);
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decoded_reg_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn, r_in.read3_data);
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r_out.read1_enable <= decoded_reg_a.reg_valid;
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r_out.read2_enable <= decoded_reg_b.reg_valid;
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r_out.read3_enable <= decoded_reg_c.reg_valid;
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case d_in.decode.length is
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when is1B =>
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length := "0001";
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when is2B =>
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length := "0010";
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when is4B =>
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length := "0100";
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when is8B =>
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length := "1000";
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when NONE =>
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length := "0000";
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end case;
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-- execute unit
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v.e.nia := d_in.nia;
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v.e.insn_type := d_in.decode.insn_type;
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v.e.read_reg1 := decoded_reg_a.reg;
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v.e.read_data1 := decoded_reg_a.data;
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v.e.read_reg2 := decoded_reg_b.reg;
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v.e.read_data2 := decoded_reg_b.data;
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v.e.read_data3 := decoded_reg_c.data;
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v.e.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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v.e.rc := decode_rc(d_in.decode.rc, d_in.insn);
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v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
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v.e.cr := c_in.read_cr_data;
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v.e.xerc := c_in.read_xerc_data;
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v.e.invert_a := d_in.decode.invert_a;
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v.e.invert_out := d_in.decode.invert_out;
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v.e.input_carry := d_in.decode.input_carry;
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v.e.output_carry := d_in.decode.output_carry;
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v.e.is_32bit := d_in.decode.is_32bit;
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v.e.is_signed := d_in.decode.is_signed;
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if d_in.decode.lr = '1' then
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v.e.lr := insn_lk(d_in.insn);
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end if;
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v.e.insn := d_in.insn;
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v.e.data_len := length;
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-- multiply unit
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v.m.insn_type := d_in.decode.insn_type;
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mul_a := decoded_reg_a.data;
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mul_b := decoded_reg_b.data;
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v.m.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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v.m.rc := decode_rc(d_in.decode.rc, d_in.insn);
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v.m.xerc := c_in.read_xerc_data;
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if v.m.insn_type = OP_MUL_L64 then
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v.m.oe := decode_oe(d_in.decode.rc, d_in.insn);
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end if;
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v.m.is_32bit := d_in.decode.is_32bit;
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if d_in.decode.is_32bit = '1' then
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if d_in.decode.is_signed = '1' then
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v.m.data1 := (others => mul_a(31));
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v.m.data1(31 downto 0) := mul_a(31 downto 0);
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v.m.data2 := (others => mul_b(31));
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v.m.data2(31 downto 0) := mul_b(31 downto 0);
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else
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v.m.data1 := '0' & x"00000000" & mul_a(31 downto 0);
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v.m.data2 := '0' & x"00000000" & mul_b(31 downto 0);
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end if;
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else
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if d_in.decode.is_signed = '1' then
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v.m.data1 := mul_a(63) & mul_a;
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v.m.data2 := mul_b(63) & mul_b;
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else
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v.m.data1 := '0' & mul_a;
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v.m.data2 := '0' & mul_b;
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end if;
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end if;
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-- divide unit
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-- PPC divide and modulus instruction words have these bits in
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-- the bottom 11 bits: o1dns 010t1 r
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-- where o = OE for div instrs, signedness for mod instrs
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-- d = 1 for div*, 0 for mod*
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-- n = 1 for normal, 0 for extended (dividend << 32/64)
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-- s = 1 for signed, 0 for unsigned (for div*)
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-- t = 1 for 32-bit, 0 for 64-bit
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-- r = RC bit (record condition code)
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v.d.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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v.d.is_modulus := not d_in.insn(8);
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v.d.is_32bit := d_in.insn(2);
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if d_in.insn(8) = '1' then
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signed_division := d_in.insn(6);
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else
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signed_division := d_in.insn(10);
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end if;
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v.d.is_signed := signed_division;
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if d_in.insn(2) = '0' then
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-- 64-bit forms
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if d_in.insn(8) = '1' and d_in.insn(7) = '0' then
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v.d.is_extended := '1';
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end if;
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v.d.dividend := decoded_reg_a.data;
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v.d.divisor := decoded_reg_b.data;
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else
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-- 32-bit forms
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if d_in.insn(8) = '1' and d_in.insn(7) = '0' then -- extended forms
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v.d.dividend := decoded_reg_a.data(31 downto 0) & x"00000000";
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elsif signed_division = '1' and decoded_reg_a.data(31) = '1' then
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-- sign extend to 64 bits
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v.d.dividend := x"ffffffff" & decoded_reg_a.data(31 downto 0);
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else
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v.d.dividend := x"00000000" & decoded_reg_a.data(31 downto 0);
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end if;
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if signed_division = '1' and decoded_reg_b.data(31) = '1' then
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v.d.divisor := x"ffffffff" & decoded_reg_b.data(31 downto 0);
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else
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v.d.divisor := x"00000000" & decoded_reg_b.data(31 downto 0);
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end if;
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end if;
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v.d.rc := decode_rc(d_in.decode.rc, d_in.insn);
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v.d.xerc := c_in.read_xerc_data;
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v.d.oe := decode_oe(d_in.decode.rc, d_in.insn);
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-- load/store unit
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v.l.update_reg := decoded_reg_a.reg;
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v.l.addr1 := decoded_reg_a.data;
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v.l.addr2 := decoded_reg_b.data;
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v.l.data := decoded_reg_c.data;
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v.l.write_reg := decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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if d_in.decode.insn_type = OP_LOAD then
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v.l.load := '1';
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else
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v.l.load := '0';
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end if;
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v.l.length := length;
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v.l.byte_reverse := d_in.decode.byte_reverse;
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v.l.sign_extend := d_in.decode.sign_extend;
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v.l.update := d_in.decode.update;
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v.l.xerc := c_in.read_xerc_data;
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-- issue control
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control_valid_in <= d_in.valid;
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control_sgl_pipe <= d_in.decode.sgl_pipe;
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gpr_write_valid <= '1' when d_in.decode.output_reg_a /= NONE else '0';
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gpr_write <= decode_output_reg(d_in.decode.output_reg_a, d_in.insn);
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gpr_a_read_valid <= decoded_reg_a.reg_valid;
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gpr_a_read <= decoded_reg_a.reg;
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gpr_b_read_valid <= decoded_reg_b.reg_valid;
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gpr_b_read <= decoded_reg_b.reg;
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gpr_c_read_valid <= decoded_reg_c.reg_valid;
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gpr_c_read <= decoded_reg_c.reg;
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cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
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v.e.valid := '0';
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v.m.valid := '0';
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v.d.valid := '0';
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v.l.valid := '0';
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case d_in.decode.unit is
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when ALU =>
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v.e.valid := control_valid_out;
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when LDST =>
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v.l.valid := control_valid_out;
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when MUL =>
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v.m.valid := control_valid_out;
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when DIV =>
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v.d.valid := control_valid_out;
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when NONE =>
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v.e.valid := control_valid_out;
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v.e.insn_type := OP_ILLEGAL;
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end case;
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if rst = '1' then
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v.e := Decode2ToExecute1Init;
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v.l := Decode2ToLoadStore1Init;
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v.m := Decode2ToMultiplyInit;
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v.d := Decode2ToDividerInit;
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end if;
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-- Update registers
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rin <= v;
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-- Update outputs
|
|
e_out <= r.e;
|
|
l_out <= r.l;
|
|
m_out <= r.m;
|
|
d_out <= r.d;
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end process;
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|
end architecture behaviour;
|