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a3857aac94
This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| include | 5 years ago | |
| libc | ||
| Makefile | ||
| bin2hex.py | ||
| head.S | ||
| main.c | ||
| sdram_init.lds.S | ||