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304 lines
10 KiB
VHDL
304 lines
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library work;
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use work.wishbone_types.all;
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use work.sim_console.all;
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entity litedram_wrapper is
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generic (
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DRAM_ABITS : positive;
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DRAM_ALINES : positive
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);
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port(
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-- LiteDRAM generates the system clock and reset
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-- from the input clkin
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clk_in : in std_ulogic;
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rst : in std_ulogic;
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system_clk : out std_ulogic;
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system_reset : out std_ulogic;
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core_alt_reset : out std_ulogic;
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pll_locked : out std_ulogic;
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-- Wishbone ports:
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wb_in : in wishbone_master_out;
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wb_out : out wishbone_slave_out;
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wb_is_csr : in std_ulogic;
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wb_is_init : in std_ulogic;
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-- Init core serial debug
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serial_tx : out std_ulogic;
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serial_rx : in std_ulogic;
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-- Misc
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init_done : out std_ulogic;
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init_error : out std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_cs_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic
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);
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end entity litedram_wrapper;
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architecture behaviour of litedram_wrapper is
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component litedram_core port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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pll_locked : out std_ulogic;
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ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_cs_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic;
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init_done : out std_ulogic;
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init_error : out std_ulogic;
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user_clk : out std_ulogic;
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user_rst : out std_ulogic;
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csr_port0_adr : in std_ulogic_vector(13 downto 0);
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csr_port0_we : in std_ulogic;
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csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
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csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
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user_port_native_0_cmd_valid : in std_ulogic;
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user_port_native_0_cmd_ready : out std_ulogic;
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user_port_native_0_cmd_we : in std_ulogic;
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user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
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user_port_native_0_wdata_valid : in std_ulogic;
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user_port_native_0_wdata_ready : out std_ulogic;
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user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0);
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user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0);
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user_port_native_0_rdata_valid : out std_ulogic;
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user_port_native_0_rdata_ready : in std_ulogic;
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user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0)
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);
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end component;
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signal user_port0_cmd_valid : std_ulogic;
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signal user_port0_cmd_ready : std_ulogic;
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signal user_port0_cmd_we : std_ulogic;
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signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0);
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signal user_port0_wdata_valid : std_ulogic;
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signal user_port0_wdata_ready : std_ulogic;
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signal user_port0_wdata_we : std_ulogic_vector(15 downto 0);
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signal user_port0_wdata_data : std_ulogic_vector(127 downto 0);
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signal user_port0_rdata_valid : std_ulogic;
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signal user_port0_rdata_ready : std_ulogic;
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signal user_port0_rdata_data : std_ulogic_vector(127 downto 0);
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signal ad3 : std_ulogic;
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signal dram_user_reset : std_ulogic;
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signal csr_port0_adr : std_ulogic_vector(13 downto 0);
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signal csr_port0_we : std_ulogic;
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signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
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signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
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signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
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signal csr_valid : std_ulogic;
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signal csr_write_valid : std_ulogic;
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signal wb_init_in : wishbone_master_out;
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signal wb_init_out : wishbone_slave_out;
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type state_t is (CMD, MWRITE, MREAD, CSR);
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signal state : state_t;
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constant INIT_RAM_SIZE : integer := 16384;
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constant INIT_RAM_ABITS :integer := 14;
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constant INIT_RAM_FILE : string := "litedram_core.init";
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type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
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impure function init_load_ram(name : string) return ram_t is
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file ram_file : text open read_mode is name;
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variable temp_word : std_logic_vector(63 downto 0);
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variable temp_ram : ram_t := (others => (others => '0'));
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variable ram_line : line;
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begin
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for i in 0 to (INIT_RAM_SIZE/8)-1 loop
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exit when endfile(ram_file);
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readline(ram_file, ram_line);
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hread(ram_line, temp_word);
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temp_ram(i) := temp_word;
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end loop;
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return temp_ram;
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end function;
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signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
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attribute ram_style : string;
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attribute ram_style of init_ram: signal is "block";
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begin
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-- BRAM Memory slave
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init_ram_0: process(system_clk)
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variable adr : integer;
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begin
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if rising_edge(system_clk) then
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wb_init_out.ack <= '0';
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if (wb_init_in.cyc and wb_init_in.stb) = '1' then
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adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3))));
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if wb_init_in.we = '0' then
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wb_init_out.dat <= init_ram(adr);
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else
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for i in 0 to 7 loop
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if wb_init_in.sel(i) = '1' then
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init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
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wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
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end if;
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end loop;
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end if;
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wb_init_out.ack <= not wb_init_out.ack;
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end if;
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end if;
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end process;
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wb_init_in.adr <= wb_in.adr;
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wb_init_in.dat <= wb_in.dat;
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wb_init_in.sel <= wb_in.sel;
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wb_init_in.we <= wb_in.we;
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wb_init_in.stb <= wb_in.stb;
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wb_init_in.cyc <= wb_in.cyc and wb_is_init;
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-- Address bit 3 selects the top or bottom half of the data
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-- bus (64-bit wishbone vs. 128-bit DRAM interface)
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--
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ad3 <= wb_in.adr(3);
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-- DRAM data interface signals
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user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
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when state = CMD else '0';
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user_port0_cmd_we <= wb_in.we when state = CMD else '0';
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user_port0_wdata_valid <= '1' when state = MWRITE else '0';
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user_port0_rdata_ready <= '1' when state = MREAD else '0';
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user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4);
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user_port0_wdata_data <= wb_in.dat & wb_in.dat;
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user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
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"00000000" & wb_in.sel;
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-- DRAM CSR interface signals. We only support access to the bottom byte
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csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
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csr_write_valid <= wb_in.we and wb_in.sel(0);
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csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
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csr_port0_dat_w <= wb_in.dat(31 downto 0);
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csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
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-- Wishbone out signals
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wb_out.ack <= '1' when state = CSR else
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wb_init_out.ack when wb_is_init = '1' else
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user_port0_wdata_ready when state = MWRITE else
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user_port0_rdata_valid when state = MREAD else '0';
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csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
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wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
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wb_init_out.dat when wb_is_init = '1' else
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user_port0_rdata_data(127 downto 64) when ad3 = '1' else
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user_port0_rdata_data(63 downto 0);
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-- We don't do pipelining yet.
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wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
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-- Reset ignored, the reset controller use the pll lock signal,
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-- and alternate core reset address set when DRAM is not initialized.
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--
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system_reset <= '0';
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core_alt_reset <= not init_done;
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-- State machine
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sm: process(system_clk)
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begin
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if rising_edge(system_clk) then
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if dram_user_reset = '1' then
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state <= CMD;
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else
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case state is
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when CMD =>
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if csr_valid = '1' then
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state <= CSR;
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elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
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state <= MWRITE when wb_in.we = '1' else MREAD;
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end if;
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when MWRITE =>
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if user_port0_wdata_ready = '1' then
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state <= CMD;
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end if;
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when MREAD =>
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if user_port0_rdata_valid = '1' then
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state <= CMD;
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end if;
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when CSR =>
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state <= CMD;
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end case;
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end if;
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end if;
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end process;
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litedram: litedram_core
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port map(
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clk => clk_in,
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rst => rst,
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pll_locked => pll_locked,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => ddram_cs_n,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p,
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ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n,
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init_done => init_done,
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init_error => init_error,
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user_clk => system_clk,
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user_rst => dram_user_reset,
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csr_port0_adr => csr_port0_adr,
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csr_port0_we => csr_port0_we,
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csr_port0_dat_w => csr_port0_dat_w,
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csr_port0_dat_r => csr_port0_dat_r,
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user_port_native_0_cmd_valid => user_port0_cmd_valid,
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user_port_native_0_cmd_ready => user_port0_cmd_ready,
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user_port_native_0_cmd_we => user_port0_cmd_we,
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user_port_native_0_cmd_addr => user_port0_cmd_addr,
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user_port_native_0_wdata_valid => user_port0_wdata_valid,
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user_port_native_0_wdata_ready => user_port0_wdata_ready,
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user_port_native_0_wdata_we => user_port0_wdata_we,
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user_port_native_0_wdata_data => user_port0_wdata_data,
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user_port_native_0_rdata_valid => user_port0_rdata_valid,
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user_port_native_0_rdata_ready => user_port0_rdata_ready,
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user_port_native_0_rdata_data => user_port0_rdata_data
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);
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end architecture behaviour;
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