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microwatt/fpga
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Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc 
This will be useful when we start needing different toplevels for
different boards.

We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
LICENSE Initial import of microwatt
arty_a7-35.xdc Merge pull request from antonblanchard/reset-rework2
clk_gen_bypass.vhd Rework SOC reset
clk_gen_mcmm.vhd Cmod A7-35 support
clk_gen_plle2.vhd Rework SOC reset
cmod_a7-35.xdc Cmod A7-35 support
firmware.hex Add a few more FPGA related files
hello_world.hex Rebuild hello world assuming a 50MHz clock
nexys-video.xdc Rename a few reset signals
nexys_a7.xdc Merge pull request from antonblanchard/reset-rework2
nodivide.patch Add a few more FPGA related files
pp_fifo.vhd Initial import of microwatt
pp_soc_memory.vhd Fix ghdl build error with pp_soc_memory
pp_soc_uart.vhd Initial import of microwatt
pp_utilities.vhd Initial import of microwatt
soc.vhdl Split FPGA toplevel from soc
soc_reset.vhdl Rework SOC reset
soc_reset_tb.vhdl Rework SOC reset
toplevel.vhdl Split FPGA toplevel from soc