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Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue ... This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		4 years ago
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VexRiscv.v	litedram: Add basic support for LiteX LiteDRAM	4 years ago
fusesoc-add-files.py	litedram: Add support for booting without BRAM	4 years ago
sim_dram_verilate.mk	litedram: Add simulation support	4 years ago
sim_litedram.vhdl	litedram: Add simulation support	4 years ago
sim_litedram_c.cpp	litedram: Add simulation support	4 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	4 years ago
wave.opt	litedram: Add an L2 cache with store queue	4 years ago
wrapper-mw-init.vhdl	litedram: Add an L2 cache with store queue	4 years ago
wrapper-self-init.vhdl	litedram: Add simulation support	4 years ago