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Paul Mackerras 9c66ab9153 MMU: Implement a page-walk cache ... This adds a page-walk cache (PWC) which stores PDEs from the page tables at the 2MB, 1GB and 512GB levels, provided they point to tables with 512 entries and map addresses below 4PB. The PWC also stores PTEs for 2MB large pages. It uses a 512 x 64b block RAM structured as 64 sets, each set using 8 words of RAM and storing 4 ways. The valid bit, page size, leaf indication (PTE vs. PDE), and PID for all 4 ways are stored in the first 64b word so that invalidate-all and invalidate-by-PID can be done in 64 cycles. The MMU test (tests/mmu/mmu.c) is modified to use a three-level tree mapping a total of 512GB, where the 1G and 2M levels can be cached in the PWC. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 days ago
..
Makefile	tests: Add a test for the MMU radix page table walks	6 years ago
head.S	tests/mmu: Add a test for a faulting load near the end of a page	3 months ago
mmu.c	MMU: Implement a page-walk cache	5 days ago
powerpc.lds	tests: mmu: Add tests for instruction translation	6 years ago