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45009ac7f3
Make the DRAM data lines and user port width configurable, also don't hard wire dependency on the wishbone data width. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
6 years ago | |
|---|---|---|
| .. | ||
| fusesoc-add-files.py | ||
| litedram-wrapper-l2.vhdl | 6 years ago | |
| sim_dram_verilate.mk | ||
| sim_litedram.vhdl | ||
| sim_litedram_c.cpp | ||
| wave.gtkw | ||
| wave.opt | ||
| wave_tb.gtkw | 6 years ago | |