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26 lines
565 B
VHDL
26 lines
565 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity clock_generator is
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generic (
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CLK_INPUT_HZ : positive := 50000000;
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CLK_OUTPUT_HZ : positive := 50000000
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);
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port (
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ext_clk : in std_logic;
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pll_rst_in : in std_logic;
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pll_clk_out : out std_logic;
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pll_locked_out : out std_logic);
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end entity clock_generator;
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architecture bypass of clock_generator is
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begin
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assert CLK_INPUT_HZ = CLK_OUTPUT_HZ severity FAILURE;
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pll_locked_out <= not pll_rst_in;
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pll_clk_out <= ext_clk;
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end architecture bypass;
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