You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
3e8a6a8fc2
Add a microwatt-verilator target that simulates the ghdl -> yosys -> verilog -> verilator path. A good test of ghdl/yosys synthesis. Because the everything is run through synthesis, the instruction image is baked into the build via the RAM_INIT_FILE generic. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
5 years ago | |
---|---|---|
.. | ||
microwatt-verilator.cpp | 5 years ago | |
uart-verilator.c | 5 years ago |