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260 lines
4.3 KiB
ArmAsm
260 lines
4.3 KiB
ArmAsm
/* Copyright 2013-2014 IBM Corp.
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* Copyrignt 2020 Shawn Anastasio
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define STACK_TOP 0x2000
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#define PVR 287
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/* Load an immediate 64-bit value into a register */
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#define LOAD_IMM64(r, e) \
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lis r,(e)@highest; \
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ori r,r,(e)@higher; \
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rldicr r,r, 32, 31; \
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oris r,r, (e)@h; \
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ori r,r, (e)@l;
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.section ".head","ax"
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/*
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* Microwatt currently enters in LE mode at 0x0, so we don't need to
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* do any endian fix ups
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*/
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. = 0
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.global _start
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_start:
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b boot_entry
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.global boot_entry
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boot_entry:
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/* setup stack */
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LOAD_IMM64(%r1, STACK_TOP - 0x100)
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LOAD_IMM64(%r12, main)
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mtctr %r12
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bctrl
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attn // terminate on exit
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b .
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/* Test addpcis with an immediate operand of 0 (min) */
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.global test_addpcis_1
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test_addpcis_1:
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mflr %r0
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std %r0, 16(%r1)
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stdu %r1, -32(%r1)
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/* get address of 1 */
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bl 1f
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1: mflr %r4
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addpcis %r5, 0
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/*
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* At this point, r5 should equal r4 + 2*4
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* return 0 if they're equal.
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*/
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addi %r4, %r4, 8
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sub %r3, %r4, %r5
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addi %r1, %r1, 32
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ld %r0, 16(%r1)
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mtlr %r0
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blr
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/* Test addpcis with an immediate operand of 0xFFFF (max) */
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.global test_addpcis_2
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test_addpcis_2:
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mflr %r0
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std %r0, 16(%r1)
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stdu %r1, -32(%r1)
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/* get address of 1 */
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bl 1f
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1: mflr %r4
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addpcis %r5, 0xFFFF
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/*
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* Add 8 to r4 to bring it in line with addpcis' NIA.
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* Then add 0xFFFF shifted and compare.
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*/
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addi %r4, %r4, 8
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addis %r4, %r4, 0xFFFF
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sub %r3, %r4, %r5
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addi %r1, %r1, 32
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ld %r0, 16(%r1)
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mtlr %r0
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blr
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/* Test reading the PVR */
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.global test_mfpvr
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test_mfpvr:
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mflr %r0
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std %r0, 16(%r1)
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stdu %r1, -32(%r1)
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/*
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* If r3 happened to already contain PVR_MICROWATT the test
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* would succeed even if the PVR is not implemented.
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*/
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LOAD_IMM64(%r3, 0xdeadbeef)
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mfpvr %r3
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addi %r1, %r1, 32
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ld %r0, 16(%r1)
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mtlr %r0
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blr
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/* Test writing the PVR does nothing */
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.global test_mtpvr
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test_mtpvr:
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mflr %r0
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std %r0, 16(%r1)
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stdu %r1, -32(%r1)
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LOAD_IMM64(%r3, 0xdeadbeef)
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mtspr PVR, %r3
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mfpvr %r3
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addi %r1, %r1, 32
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ld %r0, 16(%r1)
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mtlr %r0
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blr
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/* Test that bdnz and bdnzl update CTR and LR correctly */
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.global test_bdnzl
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test_bdnzl:
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mflr %r10
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mfcr %r11
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li %r0,0xf8
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mtctr %r0
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lis %r0,0x2000
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mtcr %r0
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addpcis %r9,0
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1: bdnztl 27,3f
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2: bdnzt 14,4f
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3: nop
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4: li %r3,1
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addi %r9,%r9,2b-1b
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mflr %r8
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cmpd %r8,%r9
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bne 9f
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mfctr %r7
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cmpdi %r7,0xf6
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bne 9f
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li %r3,0
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9: mtlr %r10
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blr
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/* Test that a load that hits stores gets the correct data */
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.global test_loadhitstore
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test_loadhitstore:
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addi %r5,%r1,-16
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ld %r0,0(%r5)
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li %r0,0
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std %r0,0(%r5)
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li %r6,0x66
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li %r7,0x77
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.balign 64
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nop
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nop
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nop
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nop
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stb %r6,2(%r5)
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stb %r7,3(%r5)
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ld %r0,0(%r5)
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sldi %r6,%r6,16
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sldi %r7,%r7,24
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or %r7,%r6,%r7
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subf %r3,%r0,%r7
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blr
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/* Test for double execution of addi */
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.balign 64
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.global test_icbi
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test_icbi:
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1: li %r3,0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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icbi 0,%r0
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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addi %r3,%r3,1
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blr
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.global test_dcbz_near_store
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test_dcbz_near_store:
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li %r0,-1
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addi %r10,%r1,-64
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# cacheline align stack pointer
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srdi %r10,%r10,6
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sldi %r10,%r10,6
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std %r0,0(%r10)
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std %r0,8(%r10)
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std %r0,16(%r10)
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std %r0,24(%r10)
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std %r0,32(%r10)
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std %r0,40(%r10)
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std %r0,48(%r10)
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std %r0,56(%r10)
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li %r3,0xa5
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# Store to same cacheline as dcbz, although it doesn't seem
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# necessary to hit the issue.
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std %r3,0(%r10)
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dcbz 0,%r10
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ld %r0,0(%r10)
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ld %r3,8(%r10)
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ld %r4,16(%r10)
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ld %r5,24(%r10)
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ld %r6,32(%r10)
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ld %r7,40(%r10)
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ld %r8,48(%r10)
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ld %r9,56(%r10)
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or %r3,%r3,%r0
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or %r3,%r3,%r4
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or %r3,%r3,%r5
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or %r3,%r3,%r6
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or %r3,%r3,%r7
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or %r3,%r3,%r8
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or %r3,%r3,%r9
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blr
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