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32 lines
679 B
VHDL
32 lines
679 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity random is
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port (
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clk : in std_ulogic;
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data : out std_ulogic_vector(63 downto 0);
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raw : out std_ulogic_vector(63 downto 0);
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err : out std_ulogic
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);
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end entity random;
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architecture behaviour of random is
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begin
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err <= '0';
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process(clk)
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variable rand : std_ulogic_vector(63 downto 0);
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variable rnd : RandomPType;
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begin
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if rising_edge(clk) then
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rand := rnd.RandSlv(64);
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data <= rand;
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raw <= rand;
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end if;
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end process;
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end behaviour;
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