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microwatt/litedram/gen-src
History
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller 
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 		4 years ago
..
sdram_init liteeth: Hook up LiteX LiteEth ethernet controller 4 years ago
arty.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
dram-init-mem.vhdl litedram: Fix DRAM init mem using too many address bits 4 years ago
generate.py litedram: Remove old "VexRiscV" based initializations 5 years ago
nexys-video.yml litedram: Remove old "VexRiscV" based initializations 5 years ago
no-init-mem.vhdl litedram: Split the init memory from the main wrapper 5 years ago
sim.yml litedram: Remove old "VexRiscV" based initializations 5 years ago