microwatt/litedram/extras
Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour
litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
..
fusesoc-add-files.py
litedram-wrapper-l2.vhdl litedram: l2: Add a few comments about litedram behaviour
sim_dram_verilate.mk
sim_litedram.vhdl
sim_litedram_c.cpp
wave.gtkw
wave.opt
wave_tb.gtkw litedram: l2: Latency improvements