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52 lines
1.2 KiB
VHDL
52 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package utils is
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function log2(i : natural) return integer;
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function log2ceil(i : natural) return integer;
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function ispow2(i : integer) return boolean;
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function round_up(i : integer; s : integer) return integer;
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end utils;
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package body utils is
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function log2(i : natural) return integer is
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variable tmp : integer := i;
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variable ret : integer := 0;
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begin
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while tmp > 1 loop
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ret := ret + 1;
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tmp := tmp / 2;
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end loop;
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return ret;
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end function;
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function log2ceil(i : natural) return integer is
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variable tmp : integer := i;
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variable ret : integer := 0;
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begin
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while tmp >= 1 loop
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ret := ret + 1;
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tmp := tmp / 2;
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end loop;
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return ret;
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end function;
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function ispow2(i : integer) return boolean is
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begin
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if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
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return true;
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else
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return false;
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end if;
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end function;
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function round_up(i : integer; s : integer) return integer is
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begin
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return ((i + (s - 1)) / s) * s;
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end function;
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end utils;
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