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29 lines
868 B
VHDL
29 lines
868 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity s25fl128s is
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generic (
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LongTimming : boolean := true;
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TimingModel : string := "";
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tdevice_PU : time := 10 ns;
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tdevice_PP256 : time := 10 ns;
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tdevice_PP512 : time := 10 ns;
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tdevice_WRR : time := 10 ns;
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UserPreload : boolean := false
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);
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PORT (
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SI : inout std_ulogic := 'Z';
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SO : inout std_ulogic := 'Z';
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SCK : in std_ulogic := 'Z';
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CSNeg : in std_ulogic := 'Z';
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RSTNeg : in std_ulogic := 'Z';
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WPNeg : inout std_ulogic := 'Z';
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HOLDNeg : inout std_ulogic := 'Z'
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);
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end entity;
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architecture behaviour of s25fl128s is
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begin
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SO <= '1';
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end architecture;
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