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290 lines
12 KiB
VHDL
290 lines
12 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.ppc_fx_insns.all;
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use work.insn_helpers.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity rotator_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end rotator_tb;
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architecture behave of rotator_tb is
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constant clk_period: time := 10 ns;
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signal ra, rs: std_ulogic_vector(63 downto 0);
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signal shift: std_ulogic_vector(6 downto 0) := (others => '0');
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signal insn: std_ulogic_vector(31 downto 0) := (others => '0');
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signal is_32bit, right_shift, arith, clear_left, clear_right: std_ulogic := '0';
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signal res: std_ulogic_vector(63 downto 0);
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signal carry_out: std_ulogic;
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signal extsw: std_ulogic;
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begin
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rotator_0: entity work.rotator
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port map (
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rs => rs,
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ra => ra,
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shift => shift,
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insn => insn,
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is_32bit => is_32bit,
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right_shift => right_shift,
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arith => arith,
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clear_left => clear_left,
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clear_right => clear_right,
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sign_ext_rs => extsw,
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result => res,
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carry_out => carry_out
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);
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stim_process: process
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variable behave_ra: std_ulogic_vector(63 downto 0);
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variable behave_ca_ra: std_ulogic_vector(64 downto 0);
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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-- TODO: Consider making debug messages visible with a command line option
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-- rather than uncommenting this line:
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-- show(display_handler, debug);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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if run("Test rlw[i]nm") then
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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extsw <= '0';
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rlwnm_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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check_equal(res, behave_ra, result("for rlwnm"));
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end loop;
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elsif run("Test rlwimi") then
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rlwimi_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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ra <= rnd.RandSlv(64);
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shift <= "00" & rnd.RandSlv(5);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
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check_equal(res, behave_ra, result("for rlwnimi"));
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end loop;
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elsif run("Test rld[i]cl") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '0';
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rldicl_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
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check_equal(res, behave_ra, result("for rldicl"));
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end loop;
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elsif run("Test rld[i]cr") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '1';
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rldicr_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("insn me = " & to_hstring(insn_me(insn)));
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debug("result = " & to_hstring(res));
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check_equal(res, behave_ra, result("for rldicr"));
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end loop;
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elsif run("Test rldic") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldic_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= '0' & rnd.RandSlv(6);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
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check_equal(res, behave_ra, result("for rldic"));
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end loop;
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elsif run("Test rldimi") then
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '1';
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clear_right <= '1';
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rldimi_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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ra <= rnd.RandSlv(64);
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shift <= '0' & rnd.RandSlv(6);
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insn <= x"00000" & '0' & rnd.RandSlv(10) & '0';
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wait for clk_period;
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behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
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check_equal(res, behave_ra, result("for rldimi"));
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end loop;
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elsif run("Test slw") then
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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slw_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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check_equal(res, behave_ra, result("for slv"));
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end loop;
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elsif run("Test sld") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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sld_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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check_equal(res, behave_ra, result("for sld"));
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end loop;
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elsif run("Test srw") then
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srw_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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check_equal(res, behave_ra, result("for srw"));
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end loop;
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elsif run("Test srd") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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srd_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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check_equal(res, behave_ra, result("for srd"));
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end loop;
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elsif run("Test sraw[i]") then
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ra <= (others => '0');
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is_32bit <= '1';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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sraw_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= '0' & rnd.RandSlv(6);
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wait for clk_period;
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behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ca_ra(63 downto 0), result("for sraw"));
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check_equal(carry_out, behave_ca_ra(64), result("for sraw carry_out"));
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end loop;
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elsif run("Test srad[i]") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '1';
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arith <= '1';
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clear_left <= '0';
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clear_right <= '0';
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srad_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= rnd.RandSlv(7);
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wait for clk_period;
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behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ca_ra(63 downto 0), result("for srad"));
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check_equal(carry_out, behave_ca_ra(64), result("for srad carry_out"));
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end loop;
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elsif run("Test extswsli") then
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ra <= (others => '0');
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is_32bit <= '0';
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right_shift <= '0';
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arith <= '0';
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clear_left <= '0';
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clear_right <= '0';
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extsw <= '1';
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extswsli_loop : for i in 0 to 1000 loop
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rs <= rnd.RandSlv(64);
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shift <= '0' & rnd.RandSlv(6);
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wait for clk_period;
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behave_ra := rs;
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behave_ra(63 downto 32) := (others => rs(31));
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behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
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to_integer(unsigned(shift))));
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debug("rs = " & to_hstring(rs));
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debug("ra = " & to_hstring(ra));
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debug("shift = " & to_hstring(shift));
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debug("result = " & to_hstring(carry_out & res));
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check_equal(res, behave_ra, result("for extswsli"));
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end loop;
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end if;
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end loop;
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test_runner_cleanup(runner);
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end process;
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end behave;
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