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			115 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			VHDL
		
	
			
		
		
	
	
			115 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			VHDL
		
	
| library vunit_lib;
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| context vunit_lib.vunit_context;
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| 
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| library ieee;
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| use ieee.std_logic_1164.all;
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| 
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| library work;
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| use work.common.all;
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| use work.wishbone_types.all;
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| 
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| entity plru_tb is
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|     generic (runner_cfg : string := runner_cfg_default);
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| end plru_tb;
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| 
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| architecture behave of plru_tb is
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|     signal clk          : std_ulogic;
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|     signal rst          : std_ulogic;
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| 
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|     constant clk_period : time := 10 ns;
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| 
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|     signal acc_en : std_ulogic;
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|     signal acc : std_ulogic_vector(2 downto 0);
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|     signal lru : std_ulogic_vector(2 downto 0);
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| 
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| begin
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|     plru0: entity work.plru
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|         generic map(
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|             BITS => 3
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|             )
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|         port map(
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|             clk => clk,
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|             rst => rst,
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| 
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|             acc => acc,
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|             acc_en => acc_en,
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|             lru => lru
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|             );
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| 
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|     clk_process: process
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|     begin
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|         clk <= '0';
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|         wait for clk_period/2;
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|         clk <= '1';
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|         wait for clk_period/2;
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|     end process;
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| 
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|     rst_process: process
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|     begin
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|         rst <= '1';
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|         wait for 2*clk_period;
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|         rst <= '0';
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|         wait;
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|     end process;
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| 
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|     stim: process
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|     begin
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|         test_runner_setup(runner, runner_cfg);
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| 
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|         wait for 4*clk_period;
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| 
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|         info("accessing 1:");
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|         acc <= "001";
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|         acc_en <= '1';
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 2:");
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|         acc <= "010";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 7:");
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|         acc <= "111";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 4:");
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|         acc <= "100";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 3:");
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|         acc <= "011";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 5:");
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|         acc <= "101";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 3:");
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|         acc <= "011";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 5:");
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|         acc <= "101";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 6:");
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|         acc <= "110";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         info("accessing 0:");
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|         acc <= "000";
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|         wait for clk_period;
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|         info("lru:" & to_hstring(lru));
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| 
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|         test_runner_cleanup(runner);
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|     end process;
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| end;
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