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76 lines
2.3 KiB
VHDL
76 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity plru is
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generic (
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BITS : positive := 2
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)
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;
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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acc : in std_ulogic_vector(BITS-1 downto 0);
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acc_en : in std_ulogic;
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lru : out std_ulogic_vector(BITS-1 downto 0)
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);
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end entity plru;
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architecture rtl of plru is
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constant count : positive := 2 ** BITS - 1;
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subtype node_t is integer range 0 to count;
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type tree_t is array(node_t) of std_ulogic;
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signal tree: tree_t;
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begin
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-- XXX Check if we can turn that into a little ROM instead that
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-- takes the tree bit vector and returns the LRU. See if it's better
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-- in term of FPGA resource usage...
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get_lru: process(tree)
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variable node : node_t;
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begin
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node := 0;
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for i in 0 to BITS-1 loop
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-- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node));
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lru(BITS-1-i) <= tree(node);
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if i /= BITS-1 then
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node := node * 2;
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if tree(node) = '1' then
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node := node + 2;
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else
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node := node + 1;
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end if;
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end if;
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end loop;
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end process;
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update_lru: process(clk)
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variable node : node_t;
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variable abit : std_ulogic;
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begin
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if rising_edge(clk) then
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if rst = '1' then
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tree <= (others => '0');
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elsif acc_en = '1' then
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node := 0;
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for i in 0 to BITS-1 loop
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abit := acc(BITS-1-i);
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tree(node) <= not abit;
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-- report "UPD: i:" & integer'image(i) & " node:" & integer'image(node) & " val" & std_ulogic'image(not abit);
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if i /= BITS-1 then
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node := node * 2;
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if abit = '1' then
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node := node + 2;
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else
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node := node + 1;
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end if;
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end if;
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end loop;
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end if;
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end if;
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end process;
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end;
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