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			299 lines
		
	
	
		
			10 KiB
		
	
	
	
		
			VHDL
		
	
			
		
		
	
	
			299 lines
		
	
	
		
			10 KiB
		
	
	
	
		
			VHDL
		
	
| library ieee;
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| use ieee.std_logic_1164.all;
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| use ieee.numeric_std.all;
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| 
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| library work;
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| 
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| package helpers is
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|     function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer;
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|     function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer;
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| 
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|     function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer;
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|     function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer;
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| 
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|     function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector;
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|     function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector;
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|     function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector;
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| 
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|     function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector;
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| 
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|     function ppc_signed_compare(a, b: signed(63 downto 0); so: std_ulogic) return std_ulogic_vector;
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|     function ppc_unsigned_compare(a, b: unsigned(63 downto 0); so: std_ulogic) return std_ulogic_vector;
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| 
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|     function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector;
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| 
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|     function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector;
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| 
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|     function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector;
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| 
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|     function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector;
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|     function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector;
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|     function edgelocation(v: std_ulogic_vector; nbits: natural) return std_ulogic_vector;
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|     function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector;
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|     function count_right_zeroes(val: std_ulogic_vector) return std_ulogic_vector;
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| end package helpers;
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| 
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| package body helpers is
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|     function fls_32 (val: std_ulogic_vector(31 downto 0)) return integer is
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|         variable ret: integer;
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|     begin
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|         ret := 32;
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|         for i in val'range loop
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|             if val(i) = '1' then
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|                 ret := 31 - i;
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|                 exit;
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|             end if;
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|         end loop;
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| 
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|         return ret;
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|     end;
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| 
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|     function ffs_32 (val: std_ulogic_vector(31 downto 0)) return integer is
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|         variable ret: integer;
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|     begin
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|         ret := 32;
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|         for i in val'reverse_range loop
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|             if val(i) = '1' then
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|                 ret := i;
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|                 exit;
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|             end if;
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|         end loop;
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| 
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|         return ret;
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|     end;
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| 
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|     function fls_64 (val: std_ulogic_vector(63 downto 0)) return integer is
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|         variable ret: integer;
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|     begin
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|         ret := 64;
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|         for i in val'range loop
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|             if val(i) = '1' then
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|                 ret := 63 - i;
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|                 exit;
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|             end if;
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|         end loop;
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| 
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|         return ret;
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|     end;
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| 
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|     function ffs_64 (val: std_ulogic_vector(63 downto 0)) return integer is
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|         variable ret: integer;
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|     begin
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|         ret := 64;
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|         for i in val'reverse_range loop
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|             if val(i) = '1' then
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|                 ret := i;
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|                 exit;
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|             end if;
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|         end loop;
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| 
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|         return ret;
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|     end;
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| 
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|     function popcnt8(val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
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|         variable ret: unsigned(3 downto 0) := (others => '0');
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|     begin
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|         for i in val'range loop
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|             ret := ret + ("000" & val(i));
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|         end loop;
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| 
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|         return std_ulogic_vector(resize(ret, val'length));
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|     end;
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| 
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|     function popcnt32(val: std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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|         variable ret: unsigned(5 downto 0) := (others => '0');
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|     begin
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|         for i in val'range loop
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|             ret := ret + ("00000" & val(i));
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|         end loop;
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| 
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|         return std_ulogic_vector(resize(ret, val'length));
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|     end;
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| 
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|     function popcnt64(val: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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|         variable ret: unsigned(6 downto 0) := (others => '0');
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|     begin
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|         for i in val'range loop
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|             ret := ret + ("000000" & val(i));
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|         end loop;
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| 
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|         return std_ulogic_vector(resize(ret, val'length));
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|     end;
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| 
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|     function cmp_one_byte(a, b: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
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|         variable ret: std_ulogic_vector(7 downto 0);
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|     begin
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|         if a = b then
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|             ret := x"ff";
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|         else
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|             ret := x"00";
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|         end if;
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| 
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|         return ret;
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|     end;
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| 
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|     function ppc_signed_compare(a, b: signed(63 downto 0); so: std_ulogic) return std_ulogic_vector is
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|         variable ret: std_ulogic_vector(2 downto 0);
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|     begin
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|         if a < b then
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|             ret := "100";
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|         elsif a > b then
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|             ret := "010";
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|         else
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|             ret := "001";
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|         end if;
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| 
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|         return ret & so;
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|     end;
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| 
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|     function ppc_unsigned_compare(a, b: unsigned(63 downto 0); so: std_ulogic) return std_ulogic_vector is
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|         variable ret: std_ulogic_vector(2 downto 0);
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|     begin
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|         if a < b then
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|             ret := "100";
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|         elsif a > b then
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|             ret := "010";
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|         else
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|             ret := "001";
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|         end if;
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| 
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|         return ret & so;
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|     end;
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| 
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|     function ra_or_zero(ra: std_ulogic_vector(63 downto 0); reg: std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
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|     begin
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|         if to_integer(unsigned(reg)) = 0 then
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|             return x"0000000000000000";
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|         else
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|             return ra;
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|         end if;
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|     end;
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| 
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|     function byte_reverse(val: std_ulogic_vector(63 downto 0); size: integer) return std_ulogic_vector is
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|         variable ret : std_ulogic_vector(63 downto 0) := (others => '0');
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|     begin
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|         -- Vivado doesn't support non constant vector slices, so we have to code
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|         -- each of these.
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|         case_0: case size is
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|             when 2 =>
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|                 for_2 : for k in 0 to 1 loop
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|                     ret(((8*k)+7) downto (8*k)) := val((8*(1-k)+7) downto (8*(1-k)));
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|                 end loop;
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|             when 4 =>
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|                 for_4 : for k in 0 to 3 loop
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|                     ret(((8*k)+7) downto (8*k)) := val((8*(3-k)+7) downto (8*(3-k)));
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|                 end loop;
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|             when 8 =>
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|                 for_8 : for k in 0 to 7 loop
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|                     ret(((8*k)+7) downto (8*k)) := val((8*(7-k)+7) downto (8*(7-k)));
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|                 end loop;
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|             when others =>
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|                 report "bad byte reverse length " & integer'image(size) severity failure;
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|         end case;
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| 
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|         return ret;
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|     end;
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| 
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|     function sign_extend(val: std_ulogic_vector(63 downto 0); size: natural) return std_ulogic_vector is
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|         variable ret : signed(63 downto 0) := (others => '0');
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|         variable upper : integer := 0;
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|     begin
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|         case_0: case size is
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|             when 2 =>
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|                 ret := resize(signed(val(15 downto 0)), 64);
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|             when 4 =>
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|                 ret := resize(signed(val(31 downto 0)), 64);
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|             when 8 =>
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|                 ret := resize(signed(val(63 downto 0)), 64);
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|             when others =>
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|                 report "bad byte reverse length " & integer'image(size) severity failure;
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|         end case;
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| 
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|         return std_ulogic_vector(ret);
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| 
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|     end;
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| 
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|     -- Reverse the order of bits in a word
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|     function bit_reverse(a: std_ulogic_vector) return std_ulogic_vector is
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|         variable ret: std_ulogic_vector(a'left downto a'right);
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|     begin
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|         for i in a'right to a'left loop
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|             ret(a'left + a'right - i) := a(i);
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|         end loop;
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|         return ret;
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|     end;
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| 
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|     -- If there is only one bit set in a doubleword, return its bit number
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|     -- (counting from the right).  Each bit of the result is obtained by
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|     -- ORing together 32 bits of the input:
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|     --  bit 0 = a[1] or a[3] or a[5] or ...
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|     --  bit 1 = a[2] or a[3] or a[6] or a[7] or ...
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|     --  bit 2 = a[4..7] or a[12..15] or ...
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|     --  bit 5 = a[32..63] ORed together
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|     function bit_number(a: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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|         variable ret: std_ulogic_vector(5 downto 0);
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|         variable stride: natural;
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|         variable bit: std_ulogic;
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|         variable k: natural;
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|     begin
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|         stride := 2;
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|         for i in 0 to 5 loop
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|             bit := '0';
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|             for j in 0 to (64 / stride) - 1 loop
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|                 k := j * stride;
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|                 bit := bit or (or a(k + stride - 1 downto k + (stride / 2)));
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|             end loop;
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|             ret(i) := bit;
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|             stride := stride * 2;
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|         end loop;
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|         return ret;
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|     end;
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| 
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|     -- Assuming the input 'v' is a value of the form 1...10...0,
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|     -- the output is the bit number of the rightmost 1 bit in v.
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|     -- If v is zero, the result is zero.
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|     function edgelocation(v: std_ulogic_vector; nbits: natural) return std_ulogic_vector is
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|         variable p: std_ulogic_vector(nbits - 1 downto 0);
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|         variable stride: natural;
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|         variable b: std_ulogic;
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|         variable k: natural;
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|     begin
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|         stride := 2;
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|         for i in 0 to nbits - 1 loop
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|             b := '0';
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|             for j in 0 to (2**nbits / stride) - 1 loop
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|                 k := j * stride;
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|                 b := b or (v(k + stride - 1) and not v(k + (stride/2) - 1));
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|             end loop;
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|             p(i) := b;
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|             stride := stride * 2;
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|         end loop;
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|         return p;
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|     end function;
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| 
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|     -- Count leading zeroes operations
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|     -- Assumes the value passed in is not zero (if it is, zero is returned)
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|     function count_right_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
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|         variable sum: std_ulogic_vector(val'left downto val'right);
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|         variable onehot: std_ulogic_vector(val'left downto val'right);
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|         variable edge: std_ulogic_vector(val'left downto val'right);
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|         variable bn, bn_e, bn_o: std_ulogic_vector(5 downto 0);
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|     begin
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|         sum := std_ulogic_vector(- signed(val));
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|         onehot := sum and val;
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|         edge := sum or val;
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|         bn_e := edgelocation(std_ulogic_vector(resize(signed(edge), 64)), 6);
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|         bn_o := bit_number(std_ulogic_vector(resize(unsigned(onehot), 64)));
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|         bn := bn_e(5 downto 2) & bn_o(1 downto 0);
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|         return bn;
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|     end;
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| 
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|     function count_left_zeroes(val: std_ulogic_vector) return std_ulogic_vector is
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|         variable rev: std_ulogic_vector(val'left downto val'right);
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|     begin
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|         rev := bit_reverse(val);
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|         return count_right_zeroes(rev);
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|     end;
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| 
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| end package body helpers;
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