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100 lines
2.7 KiB
VHDL
100 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity cache_ram is
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generic(
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ROW_BITS : integer := 5;
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WIDTH : integer := 64;
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TRACE : boolean := false;
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ADD_BUF : boolean := false
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);
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port(
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clk : in std_logic;
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rd_en : in std_logic;
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rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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rd_data : out std_logic_vector(WIDTH - 1 downto 0);
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wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
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wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
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wr_data : in std_logic_vector(WIDTH - 1 downto 0)
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);
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end cache_ram;
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architecture rtl of cache_ram is
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component RAM32_1RW1R port(
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CLK : in std_logic;
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EN0 : in std_logic;
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A0 : in std_logic_vector(4 downto 0);
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WE0 : in std_logic_vector(7 downto 0);
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Di0 : in std_logic_vector(63 downto 0);
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Do0 : out std_logic_vector(63 downto 0);
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EN1 : in std_logic;
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A1 : in std_logic_vector(4 downto 0);
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Do1 : out std_logic_vector(63 downto 0)
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);
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end component;
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signal wr_enable: std_logic;
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signal rd_data0_tmp : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0_saved : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
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signal rd_en_prev: std_ulogic;
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begin
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assert (ROW_BITS = 5) report "ROW_BITS must be 5" severity FAILURE;
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assert (WIDTH = 64) report "Must be 64 bit" severity FAILURE;
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assert (TRACE = false) report "Trace not supported" severity FAILURE;
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wr_enable <= or(wr_sel);
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cache_ram_0 : RAM32_1RW1R
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port map (
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CLK => clk,
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EN0 => wr_enable,
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A0 => wr_addr,
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WE0 => wr_sel,
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Di0 => wr_data,
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Do0 => open,
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EN1 => rd_en,
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A1 => rd_addr,
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Do1 => rd_data0_tmp
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);
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-- The caches rely on cache_ram latching the last read. Handle it here
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-- for now.
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process(clk)
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begin
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if rising_edge(clk) then
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rd_en_prev <= rd_en;
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if rd_en_prev = '1' then
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rd_data0_saved <= rd_data0_tmp;
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end if;
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end if;
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end process;
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rd_data0 <= rd_data0_tmp when rd_en_prev = '1' else rd_data0_saved;
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buf: if ADD_BUF generate
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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rd_data <= rd_data0;
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end if;
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end process;
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end generate;
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nobuf: if not ADD_BUF generate
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begin
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rd_data <= rd_data0;
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end generate;
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end architecture rtl;
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