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219 lines
6.3 KiB
VHDL
219 lines
6.3 KiB
VHDL
--
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-- This is a simple XICS compliant interrupt controller. This is a
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-- Presenter (ICP) and Source (ICS) in a single unit with no routing
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-- layer.
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--
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-- The sources have a fixed IRQ priority set by HW_PRIORITY. The
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-- source id starts at 16 for int_level_in(0) and go up from
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-- there (ie int_level_in(1) is source id 17).
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--
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-- The presentation layer will pick an interupt that is more
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-- favourable than the current CPPR and present it via the XISR and
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-- send an interrpt to the processor (via e_out). This may not be the
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-- highest priority interrupt currently presented (which is allowed
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-- via XICS)
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity xics is
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generic (
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LEVEL_NUM : positive := 16
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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int_level_in : in std_ulogic_vector(LEVEL_NUM - 1 downto 0);
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core_irq_out : out std_ulogic
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);
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end xics;
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architecture behaviour of xics is
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type reg_internal_t is record
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xisr : std_ulogic_vector(23 downto 0);
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cppr : std_ulogic_vector(7 downto 0);
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pending_priority : std_ulogic_vector(7 downto 0);
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mfrr : std_ulogic_vector(7 downto 0);
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mfrr_pending : std_ulogic;
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irq : std_ulogic;
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wb_rd_data : std_ulogic_vector(31 downto 0);
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wb_ack : std_ulogic;
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end record;
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constant reg_internal_init : reg_internal_t :=
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(wb_ack => '0',
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mfrr_pending => '0',
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mfrr => x"00", -- mask everything on reset
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irq => '0',
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others => (others => '0'));
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signal r, r_next : reg_internal_t;
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-- hardwire the hardware IRQ priority
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constant HW_PRIORITY : std_ulogic_vector(7 downto 0) := x"80";
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-- 8 bit offsets for each presentation
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constant XIRR_POLL : std_ulogic_vector(7 downto 0) := x"00";
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constant XIRR : std_ulogic_vector(7 downto 0) := x"04";
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constant RESV0 : std_ulogic_vector(7 downto 0) := x"08";
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constant MFRR : std_ulogic_vector(7 downto 0) := x"0c";
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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r <= r_next;
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end if;
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end process;
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wb_out.dat <= r.wb_rd_data;
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wb_out.ack <= r.wb_ack;
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wb_out.stall <= '0'; -- never stall wishbone
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core_irq_out <= r.irq;
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comb : process(all)
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variable v : reg_internal_t;
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variable xirr_accept_rd : std_ulogic;
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variable irq_eoi : std_ulogic;
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begin
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v := r;
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v.wb_ack := '0';
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xirr_accept_rd := '0';
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irq_eoi := '0';
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if wb_in.cyc = '1' and wb_in.stb = '1' then
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v.wb_ack := '1'; -- always ack
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if wb_in.we = '1' then -- write
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-- writes to both XIRR are the same
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case wb_in.adr(7 downto 0) is
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when XIRR_POLL =>
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report "XICS XIRR_POLL write";
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if wb_in.sel = x"f" then -- 4 bytes
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v.cppr := wb_in.dat(31 downto 24);
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elsif wb_in.sel = x"1" then -- 1 byte
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v.cppr := wb_in.dat(7 downto 0);
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end if;
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when XIRR =>
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if wb_in.sel = x"f" then -- 4 byte
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report "XICS XIRR write word:" & to_hstring(wb_in.dat);
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v.cppr := wb_in.dat(31 downto 24);
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irq_eoi := '1';
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elsif wb_in.sel = x"1" then -- 1 byte
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report "XICS XIRR write byte:" & to_hstring(wb_in.dat(7 downto 0));
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v.cppr := wb_in.dat(7 downto 0);
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else
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report "XICS XIRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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end if;
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when MFRR =>
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if wb_in.sel = x"f" then -- 4 bytes
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report "XICS MFRR write word:" & to_hstring(wb_in.dat);
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v.mfrr_pending := '1';
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v.mfrr := wb_in.dat(31 downto 24);
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elsif wb_in.sel = x"1" then -- 1 byte
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report "XICS MFRR write byte:" & to_hstring(wb_in.dat(7 downto 0));
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v.mfrr_pending := '1';
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v.mfrr := wb_in.dat(7 downto 0);
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else
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report "XICS MFRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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end if;
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when others =>
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end case;
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else -- read
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v.wb_rd_data := (others => '0');
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case wb_in.adr(7 downto 0) is
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when XIRR_POLL =>
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report "XICS XIRR_POLL read";
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if wb_in.sel = x"f" then
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v.wb_rd_data(23 downto 0) := r.xisr;
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v.wb_rd_data(31 downto 24) := r.cppr;
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elsif wb_in.sel = x"1" then
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v.wb_rd_data(7 downto 0) := r.cppr;
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end if;
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when XIRR =>
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report "XICS XIRR read";
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if wb_in.sel = x"f" then
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v.wb_rd_data(23 downto 0) := r.xisr;
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v.wb_rd_data(31 downto 24) := r.cppr;
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xirr_accept_rd := '1';
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elsif wb_in.sel = x"1" then
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v.wb_rd_data(7 downto 0) := r.cppr;
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end if;
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when MFRR =>
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report "XICS MFRR read";
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if wb_in.sel = x"f" then -- 4 bytes
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v.wb_rd_data(31 downto 24) := r.mfrr;
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elsif wb_in.sel = x"1" then -- 1 byte
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v.wb_rd_data( 7 downto 0) := r.mfrr;
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end if;
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when others =>
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end case;
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end if;
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end if;
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-- generate interrupt
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if r.irq = '0' then
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-- Here we just present any interrupt that's valid and
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-- below cppr. For ordering, we ignore hardware
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-- priorities.
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if unsigned(HW_PRIORITY) < unsigned(r.cppr) then --
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-- lower HW sources are higher priority
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for i in LEVEL_NUM - 1 downto 0 loop
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if int_level_in(i) = '1' then
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v.irq := '1';
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v.xisr := std_ulogic_vector(to_unsigned(16 + i, 24));
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v.pending_priority := HW_PRIORITY; -- hardware HW IRQs
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end if;
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end loop;
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end if;
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-- Do mfrr as a higher priority so mfrr_pending is cleared
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if unsigned(r.mfrr) < unsigned(r.cppr) then --
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report "XICS: MFRR INTERRUPT";
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-- IPI
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if r.mfrr_pending = '1' then
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v.irq := '1';
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v.xisr := x"000002"; -- special XICS MFRR IRQ source number
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v.pending_priority := r.mfrr;
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v.mfrr_pending := '0';
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end if;
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end if;
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end if;
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-- Accept the interrupt
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if xirr_accept_rd = '1' then
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report "XICS: ACCEPT" &
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" cppr:" & to_hstring(r.cppr) &
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" xisr:" & to_hstring(r.xisr) &
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" mfrr:" & to_hstring(r.mfrr);
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v.cppr := r.pending_priority;
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end if;
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if irq_eoi = '1' then
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v.irq := '0';
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end if;
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if rst = '1' then
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v := reg_internal_init;
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end if;
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r_next <= v;
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end process;
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end architecture behaviour;
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