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70 lines
1.7 KiB
VHDL
70 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cr_hazard is
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generic (
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PIPELINE_DEPTH : natural := 1
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);
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port(
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clk : in std_ulogic;
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busy_in : in std_ulogic;
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deferred : in std_ulogic;
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complete_in : in std_ulogic;
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flush_in : in std_ulogic;
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issuing : in std_ulogic;
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cr_read_in : in std_ulogic;
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cr_write_in : in std_ulogic;
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stall_out : out std_ulogic
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);
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end entity cr_hazard;
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architecture behaviour of cr_hazard is
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type pipeline_entry_type is record
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valid : std_ulogic;
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end record;
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constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
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type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
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constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
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signal r, rin : pipeline_t := pipeline_t_init;
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begin
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cr_hazard0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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cr_hazard1: process(all)
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variable v : pipeline_t;
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begin
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v := r;
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-- XXX assumes PIPELINE_DEPTH = 1
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if complete_in = '1' then
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v(1).valid := '0';
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end if;
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stall_out <= cr_read_in and (v(0).valid or v(1).valid);
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-- XXX assumes PIPELINE_DEPTH = 1
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if busy_in = '0' then
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v(1) := r(0);
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v(0).valid := '0';
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end if;
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if deferred = '0' and issuing = '1' then
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v(0).valid := cr_write_in;
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end if;
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if flush_in = '1' then
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v(0).valid := '0';
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v(1).valid := '0';
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end if;
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-- update registers
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rin <= v;
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end process;
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end;
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