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103 lines
3.0 KiB
VHDL
103 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity multiply is
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generic (
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PIPELINE_DEPTH : natural := 3
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);
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port (
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clk : in std_logic;
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m_in : in MultiplyInputType;
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m_out : out MultiplyOutputType
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal m: MultiplyInputType := MultiplyInputInit;
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type multiply_pipeline_stage is record
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valid : std_ulogic;
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data : unsigned(127 downto 0);
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end record;
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constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
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data => (others => '0'));
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type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
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constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
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type reg_type is record
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multiply_pipeline : multiply_pipeline_type;
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end record;
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signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
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signal overflow : std_ulogic;
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signal ovf_in : std_ulogic;
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begin
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multiply_0: process(clk)
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begin
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if rising_edge(clk) then
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m <= m_in;
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r <= rin;
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overflow <= ovf_in;
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end if;
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end process;
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multiply_1: process(all)
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variable v : reg_type;
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variable a, b : std_ulogic_vector(64 downto 0);
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variable prod : std_ulogic_vector(129 downto 0);
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variable d : std_ulogic_vector(127 downto 0);
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variable d2 : std_ulogic_vector(63 downto 0);
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variable ov : std_ulogic;
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begin
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v := r;
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a := (m.is_signed and m.data1(63)) & m.data1;
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b := (m.is_signed and m.data2(63)) & m.data2;
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prod := std_ulogic_vector(signed(a) * signed(b));
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v.multiply_pipeline(0).valid := m.valid;
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if m.subtract = '1' then
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v.multiply_pipeline(0).data := unsigned(m.addend) - unsigned(prod(127 downto 0));
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else
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v.multiply_pipeline(0).data := unsigned(m.addend) + unsigned(prod(127 downto 0));
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end if;
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loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
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v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
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end loop;
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d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
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ov := (or d(127 downto 63)) and not (and d(127 downto 63));
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ovf_in <= ov;
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m_out.result <= d;
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m_out.overflow <= overflow;
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m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
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rin <= v;
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end process;
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end architecture behaviour;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity short_multiply is
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port (
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clk : in std_ulogic;
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a_in : in std_ulogic_vector(15 downto 0);
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b_in : in std_ulogic_vector(15 downto 0);
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m_out : out std_ulogic_vector(31 downto 0)
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);
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end entity short_multiply;
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architecture behaviour of short_multiply is
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begin
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m_out <= std_ulogic_vector(signed(a_in) * signed(b_in));
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end architecture behaviour;
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